PDF AM45DL3208G Data sheet ( Hoja de datos )

Número de pieza	AM45DL3208G
Descripción	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Fabricantes	Advanced Micro Devices
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No Preview Available ! www.DataSheet4U.com Am45DL3208G Data Sheet September 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information DataSheet4U.com Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. DataShee DataSheet4U.com DataSheet4 U .com Publication Number 26460 Revision B Amendment +1 Issue Date March 12, 2004 1 page www.DataSheet4U.com PRELIMINARY TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. Data# Polling Algorithm .................................................. 33 MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5 RY/BY#: Ready/Busy# ............................................................ 34 Flash memory Block Diagram . . . . . . . . . . . . . . . 6 DQ6: Toggle Bit I .................................................................... 34 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. Toggle Bit Algorithm........................................................ 34 Special Package Handling Instructions .................................... 7 DQ2: Toggle Bit II ................................................................... 35 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reading Toggle Bits DQ6/DQ2 ............................................... 35 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DQ5: Exceeded Timing Limits ................................................ 35 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 DQ3: Sector Erase Timer ....................................................... 35 Table 2. Device Bus Operations—Flash Word Mode, CIOf = VIH; PSRAM Byte Mode, CIOs = VSS ....................................................11 Table 3. Device Bus Operations—Flash Byte Mode, CIOf = VSS; PSRAM Word Mode, CIOs = VCC ..................................................12 Table 4. Device Bus Operations—Flash Byte Mode, CIOf = VIL; PSRAM Byte Mode, CIOs = VSS ....................................................13 Word/Byte Configuration ........................................................ 13 Requirements for Reading Array Data ................................... 13 Table 17. Write Operation Status ................................................... 36 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 37 Figure 8. Maximum Negative Overshoot Waveform ...................... 37 Figure 9. Maximum Positive Overshoot Waveform........................ 37 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 38 CMOS Compatible .................................................................. 38 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 39 Writing Commands/Command Sequences ............................ 14 Accelerated Program Operation .......................................... 14 Figure 11. Typical ICC1 vs. Frequency............................................ 39 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 41 et4U.com Autoselect Functions ........................................................... 14 Figure 12. Test Setup.................................................................... 41 Simultaneous Read/Write Operations with Zero Latency ....... 14 Figure 13. Input Waveforms and Measurement Levels ................. 41 Standby Mode ........................................................................ 14 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 Automatic Sleep Mode ........................................................... 15 Pseudo SRAM CE#s Timing ................................................... 42 RESET#: Hardware Reset Pin ............................................... 15 Figure 14. Timing Diagram for Alternating Output Disable Mode .............................................................. 15 Table 5. Top Boot Sector Addresses .............................................15 Table 7. Bottom Boot Sector Addresses .........................................17 Sector/Sector Block Protection and Unprotection .................. 19 Between Pseudo SRAM and Flash................................................ 42 Read-Only Operations ........................................................... 43 Figure 15. Read Operation Timings ............................................... 43 Hardware Reset (RESET#) .................................................... 44 TfoarbPlero9te. cTtoiopnB/UonoptrSoetecctotiro/nSe.c..t.o..r..B...lo..c..k...A..d..d..r..e..s.s..e..s..................D....a..t..a..1S9heet4UW.cFooirgdmu/rBey1te6.CRoensefitgTuirmaitniogns ............................................................... (CIOf) .............................................. 44 45 Table 10. Bottom Boot Sector/Sector Block Addresses Figure 17. CIOf Timings for Read Operations................................ 45 for Protection/Unprotection .............................................................19 Figure 18. CIOf Timings for Write Operations................................ 45 Write Protect (WP#) ................................................................ 20 Flash Erase and Program Operations .................................... 46 Temporary Sector Unprotect .................................................. 20 Figure 1. Temporary Sector Unprotect Operation........................... 20 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 22 Figure 19. Program Operation Timings.......................................... 47 Figure 20. Accelerated Program Timing Diagram.......................... 47 Figure 21. Chip/Sector Erase Operation Timings .......................... 48 Figure 22. Back-to-back Read/Write Cycle Timings ...................... 49 Figure 23. Data# Polling Timings (During Embedded Algorithms). 49 Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 50 Figure 3. SecSi Sector Protect Verify.............................................. 23 Figure 25. DQ2 vs. DQ6................................................................. 50 Hardware Data Protection ...................................................... 23 Temporary Sector Unprotect .................................................. 51 Low VCC Write Inhibit ........................................................... 23 Figure 26. Temporary Sector Unprotect Timing Diagram .............. 51 Write Pulse “Glitch” Protection ............................................ 23 Figure 27. Sector/Sector Block Protect and Logical Inhibit ...................................................................... 23 Unprotect Timing Diagram ............................................................. 52 Power-Up Write Inhibit ......................................................... 23 Alternate CE#f Controlled Erase and Program Operations .... 53 Flash Command Definitions . . . . . . . . . . . . . . . . 27 Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program) Reading Array Data ................................................................ 27 Operation Timings.......................................................................... 54 Reset Command ..................................................................... 27 Power Up Time ....................................................................... 55 Autoselect Command Sequence ............................................ 27 Read Cycle ............................................................................. 55 Enter SecSi™ Sector/Exit SecSi Sector Figure 29. Pseudo SRAM Read Cycle—Address Controlled......... 55 Command Sequence .............................................................. 27 Read Cycle ............................................................................. 56 Byte/Word Program Command Sequence ............................. 28 Unlock Bypass Command Sequence .................................. 28 Figure 4. Program Operation .......................................................... 29 Chip Erase Command Sequence ........................................... 29 Sector Erase Command Sequence ........................................ 29 Erase Suspend/Erase Resume Commands ........................... 30 Figure 5. Erase Operation............................................................... 30 DataSheet4FUla.csohmWrite Operation Status . . . . . . . . . . . . . . . . 33 DQ7: Data# Polling ................................................................. 33 Figure 30. Pseudo SRAM Read Cycle........................................... 56 Write Cycle ............................................................................. 57 Figure 31. Pseudo SRAM Write Cycle—WE# Control ................... 57 Figure 32. Pseudo SRAM Write Cycle—CE1#s Control ................ 58 Figure 33. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 59 Flash Erase And Programming Performance . . 60 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 60 Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 60 DataShee March 12, 2004 DataSheet4 U .com Am45DL3208G 3 5 Page www.DataSheet4U.com PRELIMINARY ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am45DL320 8 G T 70 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40°C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT SECTOR T = Top boot B = Bottom boot PROCESS TECHNOLOGY G = 0.17 µm PSEUDO SRAM DEVICE DENSITY 8 = 8 Mbits et4U.com AMD DEVICE NUMBER/DESCRIPTION Am45DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL320G 32 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Pseudo Static RAM DataSheet4U.com Valid Combinations Valid Combinations list configurations planned to be supported in vol- Valid Combinations ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- Order Number Package Marking leased combinations. Am45DL3208GT70I Am45DL3208GB70I T, S M450000008 M450000009 Am45DL3208GT85I Am45DL3208GB85I T, S M45000000A M45000000B DataShee MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-3 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. DataSheet4U.com March 12, 2004 DataSheet4 U .com Am45DL3208G 9 11 Page

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