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PDF CY7C150 Data sheet ( Hoja de datos )
| Número de pieza | CY7C150 | |
| Descripción | 1Kx4 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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50
CY7C150
1Kx4 Static RAM
Features
• Memory reset function
• 1024 x 4 static RAM for control store in high-speed com-
puters
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
• CMOS for optimum speed/power
• High speed
— 10 ns (commercial)
— 12 ns (military)
• Low power
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
— 495 mW (commercial)
— 550 mW (military)
• Separate inputs and outputs
• 5-volt power supply ±10% tolerance in both commercial
and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible inputs and outputs
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D0−D3) is written into the memory location
specified on the address pins (A0 through A9).
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O0 through O3).
Functional Description
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
The CY7C150 is a high-performance CMOS static RAM de- (WE) or reset (RS) is LOW.
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
A die coat is used to insure alpha immunity.
set feature that allows the entire memory to be reset in two
memory cycles.
DataSheet4U.com
DataShee
Logic Block Diagram
D0 D1 D2 D3
DATAINPUT
CONTROL
A0
A1
A2 64 x 64
A3 ARRAY
A4
A5
COLCUMONLDUECMONDER
DECODER
RS
CS
OE
WE
O0
O1
O2
O3
C150–1
Pin Configuration
A3
A4
A5
A6
A7
A8
A9
D0
D1
O0
O1
GND
DIP/SOIC
Top View
1 24
2 23
3 22
4 21
5 20
6 7C150 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
A2
A1
A0
RS
CS
WE
OE
D3
D2
O3
O2
C150-2
A6 A7 A8 A9
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
DataSheet4U.com
Commercial
Military
Commercial
Military
7C150−10
10
90
7C150−12
12
12
90
100
7C150−15
15
15
90
100
7C150−25
25
25
90
100
7C150−35
35
90
100
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05024 Rev. **
Revised August 24, 2001
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1 page  
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Switching Waveforms (continued)
Write Cycle No2. (CS Controlled) [8,12]
ADDRESS
CE
tSA
WE
tAW
DATA IN
DATA I/O
DATA UNDEFINED
tWC
tSCS
tPWE
tHA
tSD
DATA IN VALID
tHD
tHZWE
HIGH IMPEDANCE
et4U.com Reset Cycle [13]
ADDRESS
WE
DataShtReReCt4U.com
tSAR
tSWER
tHAR
tHWER
CY7C150
C150-8
DataShee
CS
RESET
DATA I/O
tSCSR
tHCSR
tPRS
tHZRS
tLZRS
HIGH
IMPEDANCE
OUTPUT VALID ZERO
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.
13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
C150-9
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Document #: 38-05024 Rev. **
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Document Title: Cy7C150 1K x4 Static RAM
Document Number: 38-05024
REV.
Issue
ECN NO. Date
Orig. of
Change
** 106810 09/10/01 SZV
Description of Change
Change from Spec number: 38-00028 to 38-05024
CY7C150
et4U.com
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DataSheet4U.com
Document #: 38-05024 Rev. **
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11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CY7C150.PDF ] | |
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