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PDF ADSST-EM-3035 Data sheet ( Hoja de datos )
| Número de pieza | ADSST-EM-3035 | |
| Descripción | 3-Phase Electronic Energy Meter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
SALEM® Three-Phase
Electronic Energy Meter
ADSST-EM-3035
FEATURES
FUNCTIONAL BLOCK DIAGRAM
IEC 687, Class 0.5 and Class 0.2 Accuracy
ANSI C12.1
IEC 1268, Requirements for Reactive Power
SMPS
LCD DISPLAY
Configurable as Import/Export or Import Only
Simultaneous Measurement of:
Active Power and Energy—Import and Export
Reactive Power and Energy
RESISTOR
BLOCK
DSP
SPI BUS
C
Apparent Power
Power Factor for Individual Phases and Total Frequency
ADC
RMS Voltage for All Phases
RMS Current for All Phases
Harmonic Analysis for Voltage and Current
All Odd Harmonics up to 21st Order
Interface with a General Purpose Microcontroller
User-Friendly Calibration of Gain Offset and Phase and
CT
ADSST-EM-3035 FLASH
CT CHIPSET
CT RTC
OPTO
RS-232
Nonlinearity Compensation on CTs (Patent Pending)
Two Programmable Output E-Pulses
Programmable E-Pulse Constant from 1,000 Pulses/kWh
to 20,000 Pulses/kWh
15 kHz Sampling Frequency
Tamper-Proof Metering
Single 5 V Supply
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GENERAL DESCRIPTION
The ADSST-EM-3035 Chipset consists of a fast and accurate
6 channel, 16-bit sigma-delta analog-to-digital converter
ADSST-73360AR (ADC), an efficient digital signal processor
ADSST-2185KST-133 (DSP), and Metering Software. The
ADC and DSP are interfaced together to simultaneously acquire
voltage and current samples on all the three phases and perform
mathematically intensive computations to accurately calculate
the Powers, Energies, Instantaneous Quantities, and Harmonics.
The chipset could be interfaced to any general-purpose micropro-
cessor to develop state of the art polyphase or Tri-vector energy
metering solution in accordance with IEC 1036, IEC 687, or
ANSI C12.1.
All calibrations are done in digital domain and no trimming
potentiometers are required.
BUTTONS
DataShee
SALEM is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and
DataSheet4Ure.licaoblme. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
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100-Lead TQFP Package Pinout
ADSST-EM-3035
et4U.com
A4/IAD3 1
A5/IAD4 2
GND 3
A6/IAD5 4
A7/IAD6 5
A8/IAD7 6
A9/IAD8 7
A10/IAD9 8
A11/IAD10 9
A12/IAD11 10
A13/IAD12 11
GND 12
CLKIN 13
XTAL 14
VDD 15
CLKOUT 16
GND 17
VDD 18
WR 19
RD 20
BMS 21
DMS 22
PMS 23
IOMS 24
CMS 25
PIN 1
IDENTIFIER
ADSST-2185KST-133
TOP VIEW
(Not to Scale)
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75 D15
74 D14
73 D13
72 D12
71 GND
70 D11
69 D10
68 D9
67 VDD
66 GND
65 D8
64 D7/IWR
63 D6/IRD
62 D5/IAL
61 D4/IS
60 GND
59 VDD
58 D3/IACK
57 D2/IAD15
56 D1/IAD14
55 D0/IAD13
54 BG
53 EBG
52 BR
51 EBR
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ADSST-EM-3035
PIN CONFIGURATION
VINP2 1
28 VINN3
VINN2 2
27 VINP3
VINP1 3
26 VINN4
VINN1 4
25 VINP4
REFOUT
REFCAP
AVDD2
AGND2
5 24 VINN5
ADSST-
6 73360AR 23 VINP5
7 TOP VIEW 22 VINN6
8 (Not to Scale) 21 VINP6
DGND 9
DVDD 10
RESET 11
20 AVDD1
19 AGND1
18 SE
SCLK 12
17 SDI
MCLK 13
16 SDIFS
SDO 14
15 SDOFS
PIN FUNCTION DESCRIPTIONS
Mnemonic
VINP1
VINN1
VINP2
et4U.com VINN2
VINP3
VINN3
VINP4
VINN4
VINP5
VINN5
VINP6
VINN6
REFOUT
REFCAP
AVDD2
AGND2
DGND
DVDD
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Function
Mnemonic
Analog Input to the Positive Terminal of Input
Channel 1
RESET
Analog Input to the Negative Terminal of Input
Channel 1
SCLK
Analog Input to the Positive Terminal of Input
Channel 2
Analog Input to the Negative Terminal of Input
Channel 2
Analog Input to the Positive Terminal of IDnpauttaSheet4U.com
Channel 3
MCLK
Analog Input to the Negative Terminal of Input
Channel 3
SDO
Analog Input to the Positive Terminal of Input
Channel 4
Analog Input to the Negative Terminal of Input
Channel 4
SDOFS
Analog Input to the Positive Terminal of Input
Channel 5
Analog Input to the Negative Terminal of Input
Channel 5
Analog Input to the Positive Terminal of Input
Channel 6
SDIFS
Analog Input to the Negative Terminal of Input
Channel 6
Buffered Reference Output, which has a nominal value
of 1.2 V or 2.4 V, the value being dependent on the
status of Bit 5 VEN (CRC:7). This pin can be overdriven
by an external reference if required.
A Bypass Capacitor to AGND2 of 0.1 µF is required
for the on-chip reference. The capacitor should be
fixed to this pin.
SDI
SE
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Ground/Substrate Connection
Digital Power Supply Connection
AGND1
AVDD1
Function
Active Low Reset Signal. This input resets the entire chip,
resetting the control registers and clearing the digital
circuitry.
Output Serial Clock whose rate determines the serial trans-
fer rate to/from the ADSST73360AR. It is used to clock
data or control information to and from the serial port
(SPORT). The frequency of SCLK is equal to the frequency
of the master clock (MCLK) divided by
This integer number being the product
oanf tihneteegxetrenrnuaml beDr ataShee
master clock rate divider and the serial clock rate divider.
Master Clock Input. MCLK is driven from an external
clock signal.
Serial Data Output of the ADSST-73360AR. Both data
and control information may be output on this pin and are
clocked on the positive edge of SCLK. SDO is in three-
state when no information is being transmitted and when
SE is low.
Framing Signal Output for SDO Serial Transfers. The
frame sync is one bit wide and it is active one SCLK period
before the first bit (MSB) of each output word. SDOFS
is referenced to the positive edge of SCLK. SDOFS is
in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame
sync is one bit wide and it is valid one SCLK period
before the first bit (MSB) of each input word. SDIFS is
sampled on the negative edge of SCLK and is ignored
when SE is low.
Serial Data Input of the ADSST-73360AR. Both data
and control information may be input on this pin and are
clocked on the negative edge of SCLK. SDI is ignored
when SE is low.
SPORT Enable. Asynchronous input enable pin for the
SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are
ignored. SCLK is also disabled internally in order to decrease
power dissipation. When SE is brought high, the control
and data registers of the SPORT are at their original values
(before SE was brought low. However, the timing counters
and other internal registers are at their reset values.
Analog Ground Connection
Analog Power Supply Connection
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADSST-EM-3035.PDF ] | |
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