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Número de pieza | TC74AC74F | |
Descripción | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR | |
Fabricantes | Toshiba Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TC74AC74F (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! TC74AC74P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC74P,TC74AC74F,TC74AC74FN,TC74AC74FT
Dual D-Type Flip Flop with Preset and Clear
The TC74AC74 is an advanced high speed CMOS D-FLIP
FLOP fabricated with silicon gate and double-layer metal wiring
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CK pulse.
CLR and PR are independent of the CK and are
accomplished by setting the appropriate input to an “L” level.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 200 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 V to 5.5 V
• Pin and function compatible with 74F74
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC74P
TC74AC74F
TC74AC74FN
TC74AC74FT
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
TSSOP14-P-0044-0.65A
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
: 0.06 g (typ.)
1 2007-10-01
1 page TC74AC74P/F/FN/FT
AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(CK-Q, Q )
Propagation delay
time
( CLR , PR -Q, Q )
Maximum clock
frequency
Input capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpLH
tpHL
fmax
CIN
CPD
Test Condition
VCC (V)
3.3 ± 0.3
―
5.0 ± 0.5
Ta = 25°C
Min Typ. Max
― 8.2 13.9
― 6.1 8.7
―
―
―
3.3 ± 0.3
5.0 ± 0.5
―
―
8.0 13.1
5.7 8.2
3.3 ± 0.3
5.0 ± 0.5
60
100
―
120
160
5
―
―
10
(Note) ― 77 ―
Ta =
−40 to 85°C
Min Max
1.0 16.0
1.0 10.0
Unit
ns
1.0 15.0
ns
1.0 9.4
60 ―
MHz
100 ―
― 10 pF
― ― pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/2 (per F/F)
5 2007-10-01
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet TC74AC74F.PDF ] |
Número de pieza | Descripción | Fabricantes |
TC74AC74F | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR | Toshiba Semiconductor |
TC74AC74FN | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR | Toshiba Semiconductor |
TC74AC74FT | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR | Toshiba Semiconductor |
TC74AC74P | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR | Toshiba Semiconductor |
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