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PDF MTE215N10E Data sheet ( Hoja de datos )

Número de pieza MTE215N10E
Descripción Power MOSFET ( Transistor )
Fabricantes Motorola Semiconductors 
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTE215N10E/D
Designer's Data Sheet
ISOTOPTMOS E-FET.
Power Field Effect Transistor
MTE215N10E
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
2500 V RMS Isolated Isotop Package
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
Very Low Internal Parasitic Inductance
IDSS and VDS(on) Specified at Elevated Temperature
U. L. Recognized, File #E69369
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
TMOS POWER FET
215 AMPERES
100 VOLTS
RDS(on) = 0.0055 OHM
®
4
13
2
D
S
Symbol
SOT–227B
1. Source
2. Gate
3. Drain
4. Source 2
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS
VDGR
VGS
VGSM
100 Vdc
100 Vdc
± 20 Vdc
± 40 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 215 Adc
ID 136
IDM 860
Total Power Dissipation
Derate above 25°C
PD 460 Watts
3.70 W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 215 Apk, L = 0.017 mH, RG = 25 Ω,)
TJ, Tstg
EAS
– 40 to 150
400
°C
mJ
RMS Isolation Voltage
VISO
2500
Vac
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.28 °C/W
62.5
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
ISOTOP is a trademark of SGS–THOMSON Microelectronics.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1

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MTE215N10E pdf
12
QT
10
120
100
8
Q1
6
Q2
80
VGS
60
4 40
2
Q3
0
0 200
VDS
400 600 800
Qg, TOTAL GATE CHARGE (nC)
ID = 215 A
TJ = 25°C
20
0
1000 1200
Figure 8. Gate–To–Source and
Drain–To–Source Voltage versus Total Charge
1000
tr
tf
td(off)
MTE215N10E
100
td(on)
VDD = 50 V
ID = 215 A
VGS = 10 V
TJ = 25°C
10
1
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
220
200 VGS = 0 V
180 TJ = 25°C
160
140
120
100
80
60
40
20
0
0.5 0.7 0.9 1.1 1.3 1.5
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1.7
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5

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