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PDF HYB25DC512160C Data sheet ( Hoja de datos )
| Número de pieza | HYB25DC512160C | |
| Descripción | (HYB25DC512160C / HYB25DC512800C) 512M-Bit DDR SDRAM | |
| Fabricantes | Infineon Technologies Corporation | |
| Logotipo |  |
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D a t a S h e e t , Rev. 1.10, O c t . 2 0 0 5
HYB25DC512800C[E/F]
HYB25DC512160C[E/F]
512-Mbit Double-Data-Rate SDRAM
DDR SDRAM
RoHS Compliant Products
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HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
List of Tables
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Table 1
Table 2
Table 1
Table 2
Table 3
Table 4
Table 6
Table 5
Table 8
Table 7
Table 9
Table 10
Table 11
Attention:
Table 12
Table 14
Table 13
Table 15
Table 17
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information for Lead-Free(RoHS Compliant Products) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . 52
Truth Table 2: Clock Enable (CKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . 54
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Electrical Characteristics and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Pull-down and Pull-up Process Variations and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Normal Strength Pull-down and Pull-up Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Weak Strength Driver Pull-down and Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
AC Timing - Absolute Specifications for DDR400B and DDR333 . . . . . . . . . . . . . . . . . . . . . . . . . 64
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
IDD Specification and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
IDD Specification for HYB25DC512D[8a0ta0S/1h6e0eCt4[EU/.Fc]o.m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DataShee
Input Slew Rate for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input Setup & Hold Time Derating for Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input/Output Setup and Hold TIme Derating for Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input/Output Setup and Hold Derating for Rise/Fall Delta Slew Rate. . . . . . . . . . . . . . . . . . . . . . . 82
Output Slew Rate Characteristrics (×8 Devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Output Slew Rate Characteristics (×16 Devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
TFBGA Common Package Properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
Pin Configuration
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Table 1 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin Buffer
Type Type
Function
K7, 29
A0 I
SSTL Address Bus 11:0
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
A1 I
A2 I
A3 I
A4 I
A5 I
A6 I
A7 I
A8 I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Note: Provide the row address for Active commands, and the
column address and Auto Precharge bit for Read/Write
commands, to select one location out of the memory array
in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to
one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op-code during a Mode
Register Set command.
J3, 40
A9 I
SSTL
K8, 28
A10 I
SSTL
AP I
SSTL
J2, 41
A11 I
SSTL
H2, 42
A12 I
SSTL Address Signal 12
Note: Module based on 256 Mbit or larger dies
NC NC —
Note: Module based on 128 Mbit or smaller dies
F9, 17
A13 I
SSTL
Address Signal 13
DNaottaeS: 1heGebt4itUb.acsoemd module
NC NC —
Note: Module based on 512 Mbit or smaller dies
Data Signals ×8 organization
A8, 2
DQ0 I/O SSTL Data Signal Bus 7:0
B7, 5
DQ1 I/O SSTL
C7, 8
DQ2 I/O SSTL
D7, 11
DQ3 I/O SSTL
D3, 56
DQ4 I/O SSTL
C3, 59
DQ5 I/O SSTL
B3, 62
DQ6 I/O SSTL
A2, 65
DQ7 I/O SSTL
Data Strobe ×8 organisation
E3, 51
DQS
I/O
SSTL Data Strobe
Note: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write
data.
Data Mask ×8 organization
F3, 47
DM I
SSTL Data Mask
Note: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
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Data Sheet
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11 Rev. 1.10, 2005-10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYB25DC512160C.PDF ] | |
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| HYB25DC512160C | (HYB25DC512160C / HYB25DC512800C) 512M-Bit DDR SDRAM | Infineon Technologies Corporation |
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