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Número de pieza | MC14517B | |
Descripción | Dual 64-Bit Static Shift Register | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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MC14517B
Dual 64-Bit Static Shift
Register
The MC14517B dual 64–bit static shift register consists of two
identical, independent, 64–bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16–bit, 32–bit, and 48–bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.
• Diode Protection on All Inputs
• Fully Static Operation
• Output Transitions Occur on the Rising Edge of the Clock Pulse
• Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input
• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications
• Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
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Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10 mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Operating Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_ C From 65_ C To 125_ C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
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PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14517BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
14517B
AWLYYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14517BCP
MC14517BDW
PDIP–16
SOIC–16
2000/Box
47/Rail
MC14517BDWR2 SOIC–16 1000/Tape & Reel
Publication Order Number:
MC14517B/D
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VDD = VGS
MC14517B
Vout = VOH
VDD = VGS
Vout = VOL
Q16 Q32 Q48 Q64
D
C
WE
Q16 Q32 Q48 Q64
D
C
WE
D
C
WE IOH
Q16 Q32 Q48 Q64
EXTERNAL
POWER
VSS SUPPLY
(Output being tested should be in the high–logic state)
Figure 2. Typical Output Source Current
Characteristics Test Circuit
D
C
WE IOL
Q16 Q32 Q48 Q64
EXTERNAL
POWER
VSS SUPPLY
(Output being tested should be in the low–logic state)
Figure 3. Typical Output Sink Current
Characteristics Test Circuit
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PIN NO’S
CLOCK 4 (12)
WRITE 3 (13)
tsu1
DATA IN 7 (9)
tsu1
16–BIT OUTPUT 1 (15)
17–BIT INPUT
tsu1
32–BIT OUTPUT 6 (10)
33–BIT INPUT
tsu1
48–BIT OUTPUT 2 (14)
49–BIT INPUT
64–BIT OUTPUT 5 (11)
tWH
tWL
1
2
th1 th0
tsu0
th1 50%
tsu0
th0
th1
tsu0
th0
th1
tsu0
th0
16
trel
17
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VDD
20 ns
VDD
20 ns
VDD
20 ns
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
Figure 4. AC Test Waveforms
18 19
90% 33
10%
tsu
tPLH
90%
tTLH
90%
tTLH
90% 50%
10%
VOH
10%
VOHtTHL
VOL
50%
10%
tTHL
VOL
VOH
tTLH
tPLH
tTHL VOL
tTLH tTHL
VDD
50%
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
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CLOCK
DATA
EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)
D QD Q
C1
C2
DQ
C 16
3–STATE
DQ
C 17
WE
DQ
C 32
3–STATE
DQ
C 33
WE
DQ
C 48
3–STATE
DQ
C 49
WE
D
C 64 Q
3–STATE
WRITE
ENABLE
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WRITE ENABLE = 0, 16–BIT OUTPUT
WRITE ENABLE = 1, 17–BIT INPUT
32–BIT OUTPUT
33–BIT INPUT
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5
48–BIT OUTPUT
49–BIT INPUT
64–BIT OUTPUT
HIGH IMPEDANCE
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5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet MC14517B.PDF ] |
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