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PDF MC145170-2 Data sheet ( Hoja de datos )
| Número de pieza | MC145170-2 | |
| Descripción | PLL Frequency Synthesizer with Serial Interface | |
| Fabricantes | Motorola Semiconductors | |
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Freescale Semiconductor
Technical Data
MC145170-2/D
Rev. 5, 1/2005
MC145170-2
MC145170-2
PLL Frequency Synthesizer with
Serial Interface
Package Information
P Suffix
SOG Package
Case 648
1 Introduction
The new MC145170-2 is pin-for-pin compatible with the
MC145170-1. A comparison of the two parts is shown in
Table 1 on page 2. The MC145170-2 is recommended
for new designs and has a more robust power-on reset
(POR) circuit that is more responsive to momentary
power supply interruptions. The two devices are actually
the same chip with mask options for the POR circuit. The
more robust POR circuit draws approximately 20 µA
additional supply current. Note that the maximum
specification of 100 µA quiescent supply current has not
changed.
The MC145170-2 is a single-chip synthesizer capable of
direct usage in the MF, HF, and VHF bands. A special
architecture makes this PLL easy to program. Either a
bit- or byte-oriented format may be used. Due to the
patented BitGrabber™ registers, no address/steering bits
are required for random access of the three registers.
Thus, tuning can be accomplished via a 2-byte serial
transfer to the 16-bit N register.
SCALE 2:1
Package Information
D Suffix
Plastic DIP Package
Case 751B
Package Information
DT Suffix
TSSOP Package
Case 948C
Ordering Information
Device
Operating
Temperature Range
Package
MC145170P2
MC145170D2
MC145170DT2
TA = -40 to 85°C
Plastic DIP
SOG-16
TSSOP-16
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Electrical Characteristics . . . . . . . . . . . . . . . 3
3 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . 9
4 Design Considerations . . . . . . . . . . . . . . . . 18
5 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
1 page  
Electrical Characteristics
Table 4. AC Interface Characteristics
( TA = -40 to 85°C, CL = 50 pF, Input tr = tf = 10 ns, unless otherwise noted.)
Parameter
Symbol
Figure
No.
VDD Guaranteed
V Limit
Serial Data Clock Frequency (Note: Refer to Clock tw Below)
fclk
2
Maximum Propagation Delay, CLK to Dout
tPLH, tPHL
2, 6
Maximum Disable Time, Dout Active to High Impedance
tPLZ, tPHZ
3, 7
Access Time, Dout High Impedance to Active
tPZL, tPZH
3, 7
Maximum Output Transition Time, Dout
CL = 50 pF
CL = 200 pF
tTLH, tTHL
2, 6
2, 6
Maximum Input Capacitance - Din, ENB, CLK
Maximum Output Capacitance - Dout
Cin
Cout
2.7 dc to 3.0
4.5 dc to 4.0
5.5 dc to 4.0
2.7 150
4.5 85
5.5 85
2.7 300
4.5 200
5.5 200
2.7 0 to 200
4.5 0 to 100
5.5 0 to 100
2.7 150
4.5 50
5.5 50
2.7 900
4.5 150
5.5 150
- 10
- 10
Unit
MHz
ns
ns
ns
ns
ns
pF
pF
Table 5. Timing Requirements (TA = -40 to 85°C, Input tr = tf = 10 ns, unless otherwise noted.)
Parameter
Symbol
Figure
No.
VDD
V
Guaranteed
Limit
Unit
Minimum Setup and Hold Times, Din vs CLK
tsu, th
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
tsu, th, trec
Minimum Inactive-High Pulse Width, ENB
tw(H)
Minimum Pulse Width, CLK
tw
Maximum Input Rise and Fall Times, CLK
tr, tf
4
5
5
2
2
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
55 ns
40
40
135 ns
100
100
400 ns
300
300
166 ns
125
125
100 µs
100
100
Freescale Semiconductor
MC145170-2 Technical Data, Rev. 5
5
5 Page 
Pin Connections
from each pin to ground (up to a maximum of 30 pF each, including stray capacitance). An external
feedback resistor of 1.0 to 5.0 MΩ is connected directly across the pins to ensure linear operation of the
amplifier. The required connections for the components are shown in Figure 11.
5 MΩ is required across the OSCin and OSCout pins in the ac-coupled case (see Figure 9 or alternate circuit
Figure 10). OSCout is an internal node on the device and should not be used to drive any loads (i.e., OSCout
is unbuffered). However, the buffered REFout is available to drive external loads.
The external signal level must be at least 1 Vpp; the maximum frequencies are given in Table 6, the Loop
Specifications table on page 7. These maximum frequencies apply for R Counter divide ratios as indicated
in the table. For very small ratios, the maximum frequency is limited to the divide ratio times 2 MHz.
(Reason: the phase/frequency detectors are limited to a maximum input frequency of 2 MHz.)
If an external source is available which swings virtually rail-to-rail (VDD to VSS), then dc coupling can be
used. In the dc-coupled case, no external feedback resistor is needed. OSCout must be a No Connect to
avoid loading an internal node on the device, as noted above. For frequencies below 1 MHz, dc coupling
must be used. The R counter is a static counter and may be operated down to dc. However, wave shaping
by a CMOS buffer may be required to ensure fast rise and fall times into the OSCin pin. See Figure 25.
Each rising edge on the OSCin pin causes the R counter to decrement by one.
REFout
Reference Frequency Output (Pin 3)
This output is the buffered output of the crystal-generated reference frequency or externally provided
reference source. This output may be enabled, disabled, or scaled via bits in the C register (see Figure 16).
REFout can be used to drive a microprocessor clock input, thereby saving a crystal. Upon power up, the
on-chip power-on-initialize circuit forces REFout to the OSCin divided-by-8 mode.
REFout is capable of operation to 10 MHz; see the Loop Specifications table. Therefore, divide values for
the reference divider are restricted to two or higher for OSCin frequencies above 10 MHz.
If unused, the pin should be floated and should be disabled via the C register to minimize dynamic power
consumption and electromagnetic interference (EMI).
3.3 Counter Output Pins
fR
R Counter Output (Pin 9)
This signal is the buffered output of the 15-stage R counter. fR can be enabled or disabled via the C register
(patented). The output is disabled (static low logic level) upon power up. If unused, the output should be
left disabled and unconnected to minimize interference with external circuitry.
The fR signal can be used to verify the R counter's divide ratio. This ratio extends from 5 to 32,767 and is
determined by the binary value loaded into the R register. Also, direct access to the phase detector via the
OSCin pin is allowed by choosing a divide value of 1 (see Figure 17). The maximum frequency which the
phase detectors operate is 2 MHz. Therefore, the frequency of fR must not exceed 2 MHz.
Freescale Semiconductor
MC145170-2 Technical Data, Rev. 5
11
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