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PDF STK6006 Data sheet ( Hoja de datos )
| Número de pieza | STK6006 | |
| Descripción | 8051 Embedded LCD Monitor Micro Controller | |
| Fabricantes | Syntek Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de STK6006 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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STK6006
DATA SHEET
by
SYNTEK®
=========STK6006=========
8051 Embedded LDCaDtaShMeeot4nUi.ctoomr Micro-Controller
Version 1.0
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DESIGN CENTER
6F, YU FENG BLDG. 317 SUNG-CHANG RD., TAIPEI, TAIWAN, R.O.C.
TEL: 886-2-2505-6383
FAX: 886-2-2506-4323
HEADQUARTER
3F, NO.24-2, INDUSTRY E.RD., IV, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C.
TEL: 886-3-5773181
FAX: 886-3-5778010
DataSheet4U©©.cCoCmooppyyrriigghhttSSYYNNTTEEKKTTSSEEMMIICCOONNDDUUCCTTOORRCCoorrppoorraattiioonn&&LLiicceennssoorrss((22000000))..AAlll rriigghhttssrreesseerrvveedd
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STK6006
1. GENERAL DESCRIPTION
The STK6006, an LCD monitor controller, is an embedded device with 8051 CPU core, which
is in particularly designed for application to an LCD Monitor. It consists of an 8051 CPU core, a
1024-byte SRAM, 14 built PWM DACs, a VESA DDC interface, a 4-channel A/D converter, and a
64k-byte internal program Flash ROM. STK6006 works with both 5V/3.3V power supply and I/O,
and 3.3V core operating voltage.
et4U.com
2. FEATURES
• 14 channels of PWM DAC (max.)
• 31 I/O pins (max.)
• 8051 core, available for operating frequency at 12MHz with double CPU clock F/W
optional
• 1024 bytes of RAM; 64K bytes of program Flash ROM support In-System Programming
function (ISP)
• 5V/3.3V power supply and I/O; 3.3V core operating voltage
• Built-in self-test pattern generator with programmable free-running timing (15 –150KHz)
• Built-in lower power reset circuit DataSheet4U.com
• SYNC processor for composite separation/insertion, H/V polarity/frequency check, and
polarity adjustment
• Single master I2C interface for internal device to communicate
• Two slave I2C addresses; H/W auto-transfer DDC1/DDC2x data
• Feature corresponding to VESA DDC1/2B/2Bi/2B+
• 4 channels of 6-bit ADC (max.)
• A selection to protection from the Flash ROM program code
• Watchdog timer featuring programmable interval
• Package designed with 40-pin DIP, 42-pin SDIP, or 44-pin PLCC
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3. BLOCK DIAGRAM
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STK6006
AD2E = 1 → Pin “P6.2/AD2” for AD2
= 0 → Pin “P6.2/AD2” for P6.2
AD1E = 1 → Pin “P6.1/AD1” for AD1
= 0 → Pin “P6.1/AD1” for P6.1
AD0E = 1 → Pin “P6.0/AD0” for AD0
= 0 → Pin “P6.0/AD0” for P6.0
P56E = 1 → Pin “DA6/P5.6” for P5.6
= 0 → Pin “DA6/P5.6” for DA6
P55E = 1 → Pin “DA5/P5.5” for P5.5
= 0 → Pin “DA5/P5.5” for DA5
P54E = 1 → Pin “DA4/P5.4” for P5.4
= 0 → Pin “DA4/P5.4” for DA4
P53E = 1 → Pin “DA3/P5.3” for P5.3
= 0 → Pin “DA3/P5.3” for DA3
P52E = 1 → Pin “DA2/P5.2” for P5.2
= 0 → Pin “DA2/P5.2” for DA2
et4U.com P51E = 1 → Pin “DA1/P5.1” for P5.1
= 0 → Pin “DA1/P5.1” for DA1
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P50E = 1 → Pin “DA0/P5.0” for P5.0
= 0 → Pin “DA0/P5.0” for DA0
HI2CE = 1 → Pin “HSCL/P3.0/Rxd” for HSCL; pin “HSDA/P3.1/Txd” for HSDA
= 0 → Pin “HSCL/P3.0/Rxd” for P3.0/Rxd; pin “HSDA/P3.1/Txd” for P3.1/Txd
II2CE = 1 → Pin “FORDA/P3.4/T0” for FORDA; pin “FORCL/P3.5/T1” for FORCL
= 0 → Pin “FORDA/P3.4/T0” for P3.4/T0; pin “FORCL/P3.5/T1” for P3.5/T1
HCLPE = 1 → Pin “DA7/HCLAMP” for HSYNC clamp pulse output
= 0 → Pin “DA7/HCLAMP” for DA7
P42E = 1 → Pin “STO/P4.2” for P4.2
= 0 → Pin “STO/P4.2” for STO
P41E = 1 → Pin “HBLANK/P4.1” for P4.1
= 0 → Pin “HBLANK/P4.1” for HBLANK.
P40E = 1 → Pin “VBLANK/P4.0” for P4.0.
= 0 → Pin “VBLANK/P4.0” for VBLANK.
P56oe = 1 → P5.6 used as output pin.
= 0 → P5.6 used as input pin.
P55oe = 1 → P5.5 used as output pin.
= 0 → P5.5 used as input pin.
DataSheet4UP.5c4oome = 1 → P5.4 used as output pin.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STK6006.PDF ] | |
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