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PDF P87C654X2 Data sheet ( Hoja de datos )
| Número de pieza | P87C654X2 | |
| Descripción | 80C51 8-bit microcontroller family | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Product data
Supersedes data of 2003 Feb 13
2004 Apr 20
Philips
Semiconductors
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Philips Semiconductors
80C51 8-bit microcontroller family 16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
Product data
P83C654X2/P87C654X2
LOGIC SYMBOL
VCC
XTAL1
VSS
XTAL2
RST
EA/VPP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
T1
WR
RD
ADDRESS AND
DATA BUS
T2
T2EX
SCL0
SDA0
SCL1
SDA1
ADDRESS BUS
SU01730
PINNING
Plastic Leaded Chip Carrier
6 1 40
7 39
LCC
17 29
Pin Function
1 NIC1
2 P1.0/T2
3 P1.1/T2EX
4 P1.2/ECI
5 P1.3
6 P1.4
7 P1.5
8 P1.6/SCL0
9 P1.7/SDA0
10 RST
11 P3.0/RxD
12 VSS32
13 P3.1/TxD
14 P3.2/INT0
15 P3.3/INT1
18 28
Pin Function
16 P3.4/T0
17 P3.5/T1
18 P3.6/WR
19 P3.7/RD
20 XTAL2
21 XTAL1
22 VSS1
23 NIC1
24 P2.0/A8
25 P2.1/A9
26 P2.2/A10
27 P2.3/A11
28 P2.4/A12
29 P2.5/A13
30 P2.6/A14
Pin Function
31 P2.7/A15
32 PSEN
33 ALE
34 VSS22
35 EA/VPP
36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 VCC
SU01729
1. No internal connection
2. May be left open, but it is recommended that VSS2 and VSS3 be
connected to GND to improve EMC performance
Plastic Quad Flat Pack
44
34
1 33
LQFP
11 23
Pin Function
1 P1.5
2 P1.6/SCL0
3 P1.7/SDA0
4 RST
5 P3.0/RxD
6 VSS32
7 P3.1/TxD
8 P3.2/INT0
9 P3.3/INT1
10 P3.4/T0
11 P3.5/T1
12 P3.6/WR
13 P3.7/RD
14 XTAL2
15 XTAL1
12 22
Pin Function
16 VSS1
17 NIC1
18 P2.0/A8
19 P2.1/A9
20 P2.2/A10
21 P2.3/A11
22 P2.4/A12
23 P2.5/A13
24 P2.6/A14
25 P2.7/A15
26 PSEN
27 ALE
28 VSS22
29 EA/VPP
30 P0.7/AD7
Pin Function
31 P0.6/AD6
32 P0.5/AD5
33 P0.4/AD4
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 VCC
39 NIC1
40 P1.0/T2
41 P1.1/T2EX
42 P1.2/ECI
43 P1.3
44 P1.4
SU01731
1. No internal connection
2. May be left open, but it is recommended that VSS2 and VSS3 be
connected to GND to improve EMC performance
2004 Apr 20
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Philips Semiconductors
80C51 8-bit microcontroller family 16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
Product data
P83C654X2/P87C654X2
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. Minimum and maximum
high and low times specified in the data sheet must be observed.
This device is configured at the factory to operate using 12 clock
periods per machine cycle, referred to in this datasheet as “12-clock
mode”. It may be optionally configured on commercially available
EPROM programming equipment to operate at 6 clocks per machine
cycle, referred to in this datasheet as “6-clock mode”. (This yields
performance equivalent to twice that of standard 80C51 family
devices). Also see next page.
RESET
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (12 oscillator periods in 6-clock mode, or 24
oscillator periods in 12-clock mode), while the oscillator is running.
To insure a good power-on reset, the RST pin must be HIGH long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VCC and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above VIH (min.) is applied to RESET. The
value on the EA pin is latched when RST is deasserted and has no
further effect.
LOW POWER MODES
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power-down mode is suggested.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power-down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked power-down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2 V and care must be taken to return VCC to the
minimum specified operating voltages before the Power-down mode
is terminated.
Either a hardware reset or external interrupt can be used to exit from
power-down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To properly terminate power-down, the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin LOW restarts the
oscillator but bringing the pin back HIGH completes the exit. Once
the interrupt is serviced, the next instruction to be executed after
RETI will be the one following the instruction that put the device into
power-down.
POWER-OFF FLAG
The Power-Off Flag (POF) is set by on-chip circuitry when the VCC
level on the P8xC654X2 rises from 0 to 5 V. The POF bit can be set
or cleared by software allowing a user to determine if the reset is the
result of a power-on or a warm start after power-down. The VCC
level must remain above 3 V for the POF to remain unaffected by
the VCC level.
Low-Power EPROM operation (LPEP)
The EPROM array contains some analog circuits that are not
required when VCC is less than 4 V, but are required for a VCC
greater than 4 V. The LPEP bit (AUXR.4), when set, will power-down
these analog circuits resulting in a reduced supply current. This bit
should be set ONLY for applications that operate at a VCC less than
4 V.
Design Consideration
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a
port pin or to external memory.
ONCE™ Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE LOW while the device is in reset and PSEN is HIGH;
2. Hold ALE LOW as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
HIGH. The oscillator circuit remains active. While the device is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-Out
A 50 % duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at
a 16 MHz operating frequency (61 Hz to 4 MHz in 12-clock mode).
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet P87C654X2.PDF ] | |
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