PDF HM5117400B Data sheet ( Hoja de datos )

Número de pieza	HM5117400B
Descripción	4M DRAM
Fabricantes	Hitachi
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No Preview Available ! www.DataSheet4U.com www.DataSheet4U.com DataSheet4 U .com www.DataSheet4U.com 1 page www.DataSheet4U.com HM5117400B Series Block Diagram RAS CAS WE OE I/O 4 I/O Buffer 4 I/O 3 I/O Buffer 3 Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus www.DataSheet4U.comColumn decoder & driver Column decoder & driver Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus I/O Buffer 2 I/O 2 I/O Buffer 1 I/O 1 Address A0 to A10 Da4taSheet4 U .com www.DataSheet4U.com 5 Page www.DataSheet4U.com HM5117400B Series Fast Page Mode Read-Modify-Write Cycle HM5117400B -6 -7 Parameter Symbol Min Max Min Fast page mode read-modify-write tPRWC cycle time 85 — 96 WE delay time from CAS precharge tCPW 60 — 68 Max — — -8 Min Max 105 — 75 — Unit Notes ns ns 14 Test Mode Cycle*19 Parameter Test mode WE setup time Test mode WE hold time HM5117400B -6 -7 Symbol Min Max Min tWTS 0 — 0 tWTH 10 — 10 Max — — -8 Min Max 0— 10 — Unit Notes ns ns Refresh Parameter www.DaStymaboSl heMeax t4U.cUnoit m Note Refresh period tREF 32 ms 2048 cycles Refresh period (L-version) tREF 128 ms 2048 cycles Notes: 1. AC measurements assume tT = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. Da1ta0Sheet4 U .com www.DataSheet4U.com 11 Page

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