|
|
PDF SCF5250 Data sheet ( Hoja de datos )
| Número de pieza | SCF5250 | |
| Descripción | SCF5250 Integrated ColdFire Microprocessor | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SCF5250 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Freescale Semiconductor
Data Sheet
Document Number: SCF5250EC
Rev. 1.1, 04/2005
SCF5250 Integrated ColdFire®
Microprocessor Data Sheet
1 Introduction
Table of Contents
1 Introduction..........................................................1
This document provides an overview of the SCF5250
www.DataSheet4U.comColdFire® processor and general descriptions of
2 SCF5250 Block Diagram .....................................8
3 Documentation ....................................................8
4 Signal Descriptions..............................................9
SCF5250 features and its various modules.
5 Electrical Characteristics ...................................21
The SCF5250 was designed as a system
6 Pin-Out and Package Information .....................38
controller/decoder for compressed audio music players,
especially portable and automotive CD and hard disk
drive players. The 32-bit ColdFire core with Enhanced
Multiply Accumulate (EMAC) unit provides optimum
performance and code density for the combination of
control code and signal processing required for audio
decoding and post processing, file management, and
system control.
Low power features include a hardwired CD ROM
decoder, advanced 0.13um CMOS process technology,
1.2V core power supply, and on-chip 128KByte SRAM
that enables Windows Media Audio (WMA) decoding
without the need for external DRAM in CD applications.
The SCF5250 is also an excellent general purpose
system controller with over 110 Dhrystone 2.1 MIPS @
120MHz performance at a very competitive price. The
integrated peripherals and enhanced MAC unit allow the
© Freescale Semiconductor, Inc., 2004. All rights reserved.
www.DataSheet4U.com
1 page  
www.DataSheet4U.com
Introduction
• Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
• Third-layer error encoding needs to be done in software. This can use approximately 5-10 Mhz of
performance for single-speed.
1.2.13 Dual UART Module
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats
can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte
receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function from a programmable prescaler. You can select full
duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs
can interrupt the CPU on various normal or error-condition events.
1.2.14 Queued Serial Peripheral Interface QSPI
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to
16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
15 Mbits/second are possible at a CPU clock of 120 MHz. The QSPI supports master mode operation only.
1.2.15 Timer Module
www.DataSheet4U.comThe timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer.
Timer0 has an external pin TOUT0, which can be used in Output Compare mode. This mode triggers an
external signal or interrupts the CPU when the timer reaches a set value, and can also generate waveforms
on TOUT0.
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock
/ 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.
1.2.16 IDE and SmartMedia Interfaces
The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a
minimum of external hardware. The external hardware consists of bus buffers for address and data and are
intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE
bus. The control signals for the buffers are generated in the SCF5250.
1.2.17 Analog/Digital Converter (ADC)
The six channel ADC is a based on the Sigma-Delta concept with 12-bit resolution. Both the analogue
comparator and digital sections of the ADC are provided internally. An external integrator circuit
(resistor/capacitor) is required, which is driven by the ADC output. A software interrupt is provided when
the ADC measurement cycle is complete.
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
Freescale Semiconductor
5
www.DataSheet4U.com
5 Page 
www.DataSheet4U.com
Signal Descriptions
Table 3. SCF5250 Signal Index (continued)
Signal Name
Mnemonic
Function
Serial input
EF/GPIO6
error flag serial in
Serial input
CFLG/GPIO5
C-flag serial in
Subcode clock
RCK/QSPI_DIN/QSPI_DOUT/
GPIO26
audio interfaces subcode clock
Subcode sync
QSPI_DOUT/SFSY/GPIO27
audio interfaces subcode sync
Subcode data
QSPI_CLK/SUBR/GPIO25
audio interfaces subcode data
Clock frequency trim
XTRIM/GPIO0
clock trim control
Audio clocks out
MCLK1/GPIO11
QSPI_CS2/MCLK2/GPIO24
DAC output clocks
Audio clock in
LRCK3/GPIO43/AUDIO_CLOCK
Optional Audio clock Input
MemoryStick/SecureDigita EBUIN3/CMD_SDIO2/GPIO14
l interface
Secure Digital command lane
MemoryStick interface 2 data i/o
EBUIN2/SCLK_OUT/GPIO13
Clock out for both MemoryStick
interfaces and for Secure Digital
DDATA0/CTS1/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0
MemoryStick interface 1 data i/o
SCL0/SDATA1_BS1/GPIO41
SecureDigital serial data bit 1
MemoryStick interface 1 strobe
DDATA1/RTS1/SDATA2_BS2/GPIO2 SecureDigital serial data bit 2
MemoryStick interface 2 strobe
www.DataSheet4U.comSDA0/SDATA3/GPIO42
Reset output signal
SecureDigital serial data bit 3
ADC IN
ADIN0/GPI52
ADIN1/GPI53
ADIN2/GPI54
ADIN3/GPI55
ADIN4/GPI56
ADIN5/GPI57
Analog to Digital converter input
signals
ADC OUT
ADREF
ADOUT/SCLK4/GPIO58
Analog to digital convertor output
signal. Connect to ADREF via
integrator network.
QSPI clock
QSPI_CLK/SUBR/GPIO25
QSPI clock signal
QSPI data in
RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data input
QSPI data out
RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data out
QSPI_DOUT/SFSY/GPIO27
QSPI chip selects
QSPI_CS0/EBUIN4/GPIO15
QSPI_CS1/EBUOUT2/GPIO16
QSPI_CS2/MCLK2/GPIO24
CS1/QSPI_CS3/GPIO28
QSPI chip selects
Crystal in
CRIN
Crystal input
Crystal out
CROUT
Crystal Out
Reset In
RSTI
Processor Reset Input
Freescale Test Mode
TEST[2:0]
TEST pins.
Linear regulator output LINOUT
outputs 1.2 V to supply core
Input/
Output
In/Out
In/Out
In/Out
In/Out
In/Out
Out
Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In
In/Out
In/Out
In/Out
In/Out
In/Out
In
Out
In
In
Out
Reset
State
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
Freescale Semiconductor
11
www.DataSheet4U.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SCF5250.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SCF5250 | SCF5250 Integrated ColdFire Microprocessor | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |