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PDF SPF-3043 Data sheet ( Hoja de datos )

Número de pieza SPF-3043
Descripción Low Noise Phemt GAAS Fet
Fabricantes Sirenza 
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Product Description
Sirenza Microdevices’ SPF-3043 is a high performance
0.25µm pHEMT Gallium Arsenide FET. This 300µm device is
ideally biased at 3V,20mA for lowest noise performance and
battery powered requirements. At 5V,40mA the device can
deliver OIP3 of 32dBm. It provides ideal performance as a
driver stage in many commercial and industrial LNA
applications.
35
30
25
20
15
10
5
0
Typical Gain Performance
3V,20mA
5V,40mA
Gain
Gmax
246
Frequency (GHz)
8
10
Preliminary
SPF-3043
Low Noise pHEMT GaAs FET
Product Features
• DC-10 GHz Operation
• 0.5 dB NFMIN @ 2 GHz
• 22 dB GMAX @ 2 GHz
• +32 dBm OIP3 (5V,40mA)
• +20 dBm P1dB (5V,40mA)
• Low Current, Low Cost
• Apps circuits available for key bands
Applications
• Analog and Digital Wireless Systems
• 3G, Cellular, PCS
• Fixed Wireless, Pager Systems
• Driver Stage for Low Power Applications
Symbol
GMAX
www.DataSheet4U.comDevice Characteristics
Test Conditions
VDS=5V, IDQ=40mA, 25ºC
(unless otherwise noted)
Test
Frequency
Units
Min.
Typ.
Maximum Available Gain
ZS=ZS*, ZL=ZL*
0.9 GHz
1.9 GHz
dB
26.5
23.4
Max.
NFMIN Minimum Noise Figure
ZS=ΓOPT , ZL=ZL*
0.9 GHz
1.9 GHz
dB
0.32
0.54
S21 Insertion Gain [1]
NF Noise Figure [2]
ZS=ZL= 50
LNA Application Circuit Board
0.9 GHz
1.9 GHz
dB 18.5 20.0 21.5
dB 1.05 1.40
Gain Gain [2]
LNA Application Circuit Board
1.9 GHz
dB 14.0 15.3
OIP3
P1dB
VP
IDSS
gm
BVGSO
BVGDO
Rth
Output Third Order Intercept Point [2] LNA Application Circuit Board
Output 1dB Compression Point [2] LNA Application Circuit Board
Pinchoff Voltage [1]
Saturated Drain Current [1]
Transconductance [1]
Gate-Source Breakdown Voltage [1]
Gate-Drain Breakdown Voltage [1]
Thermal Resistance
VDS= 2V, IDS= 0.1 mA
VDS= 2V, VGS= 0 V
VDS= 2V, VGS= 0 V
IGS= 0.03 mA, drain open
IGD= 0.03 mA, source open
junction-to-lead
1.9 GHz
1.9 GHz
dBm
dBm
V
mA
mS
V
V
ºC/W
26.0
15.0
-1.1
30
90
28.5
17.0
-0.8
60
150
-10
-10
150
-0.5
120
-8
-8
VDS Operating Voltage
drain-source
V 5.5
IDS Operating Current
drain-source
mA 55
[1] 100% tested - DC parameters tested on-wafer, insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test.
[2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from 500 devices across 5 wafers, 3 wafer lots. The
test fixture is an engineering application circuit board (parts are pressed down on the circuit board). The application circuit represents a trade-off between the optimal noise
match and input return loss.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are
subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not
authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems.
Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
1
http://www.sirenza.com
www.DEaDtSa-1S0h17e72eRte4v CU.com

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