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PDF CY62158EV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62158EV30 | |
| Descripción | 8M-Bit Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62158EV30 MoBL®
8-Mbit (1024 K × 8) Static RAM
8-Mbit (1024 K × 8) Static RAM
Features
■ Very high speed: 45 ns
❐ Wide voltage range: 2.20 V–3.60 V
■ Pin compatible with CY62158DV30
■ Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A
■ Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed/power
■ Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE1 HIGH or
CE2 LOW). The eight input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE1 HIGH or CE2 LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE1 LOW and
CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the I/O pins. See Truth Table on page
11 for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
WE
OE
DATA IN DRIVERS
1024K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IIO/O0 0
IIO/O1 1
IIO/O2 2
IIO/O3 3
IIO/O4 4
IIO/O5 5
IIO/O6 6
IIO/O7 7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05578 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 28, 2014
1 page  
CY62158EV30 MoBL®
Capacitance
Parameter [8]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [8]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max Unit
10 pF
10 pF
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
48-ball BGA 44-pin TSOP II Unit
72
76.88
C/W
8.86
13.52
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
R2
VCC
GND
10%
Rise Time: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
2.5 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Unit
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05578 Rev. *J
Page 5 of 18
5 Page 
CY62158EV30 MoBL®
Truth Table
CE1
H
X[29]
L
L
L
CE2
X[29]
L
H
H
H
WE
X
X
H
L
H
OE Inputs/Outputs
X High Z
X High Z
L Data Out
X Data In
H High Z
Mode
Deselect/Power down
Deselect/Power down
Read
Write
Selected, Outputs Disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Note
29. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05578 Rev. *J
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY62158EV30.PDF ] | |
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