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PDF MC14LC5436A Data sheet ( Hoja de datos )
| Número de pieza | MC14LC5436A | |
| Descripción | Low Power Dual Tone Multiple Frequency Receiver | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Low-Power Dual Tone
Multiple Frequency Receiver
The MC145436A is a low–power and improved input sensitivity version of the
MC14LC5436.
The MC145436A is a silicon gate CMOS LSI device containing the filter and
decoder for detection of a pair of tones conforming to the DTMF standard with
outputs in hexadecimal. Switched capacitor filter technology is used together
with digital circuitry for the timing control and output circuits. The MC145436A
provides excellent power line noise and dial tone rejection and is suitable for
applications in central office equipment, PABX, and keyphone systems, remote
control equipment and consumer telephony products.
The MC145436A offers the following performance features:
• Single + 5 V Power Supply
• Detects All 16 Standard Digits
• Uses Inexpensive 3.58 MHz Crystal
• Provides Guard Time Controls to Improve Speech Immunity
• Output in 4–Bit Hexadecimal Code
• Built–In 60 Hz and Dial Tone Rejection
• Pin Compatible with SSI–204, MC145436, and MC14LC5436
• Functional and Applicational Compatible with MC145436 and
MC14LC5436
Order this document
by MC145436A/D
MC145436A
14
1
P SUFFIX
PLASTIC DIP
CASE 646
16
1
DW SUFFIX
SOG PACKAGE
CASE 751G
ORDERING INFORMATION
MC145436AP Plastic DIP
MC145436ADW SOG Package
PIN ASSIGNMENTS
PDIP
D2 1
14 D4
D1 2
13 D8
ENB 3
VDD 4
GT 5
Xen 6
Ain 7
12 DV
11 ATB
10 Xin
9 Xout
8 GND
SOG
D2 1
16 D4
D1 2
15 D8
ENB 3
14 DV
VDD 4
NC 5
13 NC
12 ATB
GT 6
Xen 7
Ain 8
11 Xin
10 Xout
9 GND
NC = NO CONNECTION
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
1/96
©MOMoTtoOroRla,OInLc.A1996
MC145436A
1
1 page  
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PIN DESCRIPTIONS
VDD
Positive Power Supply (PDIP, SOG — Pin 4)
The digital supply pin, which is connected to the positive
side of the power supply.
VSS
Ground (PDIP — Pin 8, SOG — Pin 9)
Ground return pin is typically connected to the system
ground.
D1, D2, D4, D8
Data Output (PDIP — Pins 2, 1, 14, 13; SOG — Pins 2, 1,
16, 15)
These digital outputs provide the hexadecimal codes cor-
responding to the detected digit. The digital outputs become
valid after a tone pair has been detected and are cleared
when a valid pause is timed. See Table 1 for hexadecimal
codes.These output pins are high impedance when the
enable pin is at logic 0.
ENB
Enable (PDIP, SOG — Pin 3)
Outputs D1, D2, D4, D8 are enabled when ENB is at a
logic 1, and high impedance (disabled) when ENB is at a
logic 0.
GT
Guard Time (PDIP — Pin 5, SOG — Pin 6)
The guard time control input provides two sets of detected
time and release time, both within the allowed ranges of tone
on and tone off (see Figure 1). A longer tone detect time
rejects signals too short to be considered valid. With GT = 1,
talk off performance is improved, since it reduces the prob-
ability that tones simulated by speech will maintain signal
conditions long enough to be accepted. In addition, a shorter
release time reduces the probability that a pause simulated
by an interrupt in speech will be detected as a valid pause.
On the other hand, a shorter tone detect time with a long
Digit
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
Table 1. Hexadecimal Codes
Output Code
D8 D4 D2
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
000
D1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MOTOROLA
release time would be appropriate for an extremely noisy
environment where fast acquisition time and immunity to
dropouts would be required. In general, the tone signal time
generated by a telephone is 100 ms, nominal, followed by a
pause of about 100 ms. A high–to–low or low–to–high tran-
sition on the GT pin resets the internal logic and the
MC145436A is immediately ready to accept a new tone
input. If left open, this pin is internally pulled to ground.
Xen
Oscillator Enable (PDIP — Pin 6, SOG — Pin 7)
A logic 1 on Xen enables the on–chip crystal oscillator.
When using alternate time base from the ATB pin, Xen should
be tied to VSS.
Ain
Analog Input (PDIP — Pin 7, SOG — Pin 8)
This pin accepts the analog input and is internally biased
so that the input signal may be ac coupled. The input may be
dc coupled so long as it does not exceed the positive supply
(see Figure 2).
Xin/Xout
Oscillator In and Oscillator Out (PDIP — Pins 10, 9;
SOG — Pins 11, 10)
These pins connect to an internal crystal oscillator. In oper-
ation, a parallel resonant crystal is connected from Xin to
Xout, as well as a 1 MΩ resistor in parallel with the crystal.
When using the alternate clock source from ATB, Xin should
be tied to VDD.
ATB
Alternate Time Base (PDIP — Pin 11, SOG — Pin 12)
This pin serves as a frequency reference when more than
one MC145436A is used, so that only one crystal is required
for multiple MC145436As. When doing so, all ATB pins
should be tied together as shown in Figure 3. When only one
MC145436A is used, this pin should be left unconnected.
The output frequency of ATB is 447.4 kHz.
DV
Data Valid (PDIP — Pin 12, SOG — Pin 14)
DV signals a detection by going high after a valid tone pair
is sensed and decoded at output pins D1, D2, D4, D8. DV
remains high until a loss of the current DTMF signal occurs
or until a transition in GT occurs.
GUARD TIME
5
VDD
Figure 1. Guard Time
MC145436A
5
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