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PDF CXD1944R Data sheet ( Hoja de datos )
| Número de pieza | CXD1944R | |
| Descripción | IEEE1394 3-port 200Mbps Cable Transceiver/Arbiter | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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PRELIMINARY
CXD1944R
IEEE1394 3-port 200Mbps Cable Transceiver/Arbiter
Description
The CXD1944R is a PHY chip which supports
100/200Mbps speeds and performs cable interface and
bus arbitration. It conforms to the high performance seri-
al bus IEEE1394-1995 standard. The structure is 0.4µm
CMOS and it operates on a single 3.3V power supply.
64 pin LQFP (plastic)
Features
• Conforms to IEEE1394-1995
• Single 3.3V power supply
• Supports 100/200Mbps speeds
• Automatic power down for unused ports
• Power down mode to conserve energy
• Supports short reset operation
• Supports ping for optimization of a Gap_count
Absolute Maximum Ratings
• Supply voltage
VDD –0.5 to +4.6
V
• Input voltage
VI VSS –0.5 to VDD +0.5 V
• Output voltage
VO VSS –0.5 to VDD +0.5 V
• Operating temperature Ta
–20 to +70
°C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
1000
mW
Operating Conditions
• Supply voltage
VDD
• Operating temperature Ta
3.0 to 4.5
–20 to +75
V
°C
Package
64-pin plastic LQFP (VQFP)
Applications
When used with a LINK chip (e.g. CXD1940R), allows
configuration of a high-speed digital serial interface.
Structure
0.4µm CMOS monolithic IC
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Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication
or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
–1– PE96431–ST
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CXD1944R
Pin No.
35
36
37
38
39
40
41
42
43
44
45
46
Symbol
TPA3–
TPA3+
TPB2–
TPB2+
TPA2–
TPA2+
AVSS
TPB1–
TPB1+
TPA1–
TPA1+
TB1
47 TB2
48 TB3
49 AVSS
50 AVSS
51 AVDD
52 PLLVSS
53 PLLVSS
54 FLT
55 PLLVDD
56 XI
57 XO
58 DVDD
59 R0
60 R1
61 AVSS
62 XISO
63 AVSS
64 AVSS
I/O
I/O(A)
I/O(A)
I/O(A)
I/O(A)
I/O(A)
I/O(A)
Supply
I/O(A)
I/O(A)
I/O(A)
I/O(A)
O(A)
O(A)
O(A)
Supply
Supply
Supply
Supply
Supply
O(A)
Supply
I(A)
O(A)
Supply
I(A)
O(A)
Supply
I
Supply
Supply
Description
Port3, Cable Pair A–.
Port3, Cable Pair A+.
Port2, Cable Pair B–.
Port2, Cable Pair B+.
Port2, Cable Pair A–.
Port2, Cable Pair A+.
Analog circuit power ground.
Port1, Cable Pair B–.
Port1, Cable Pair B+.
Port1, Cable Pair A–.
Port1, Cable Pair A+.
Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power
down. Corresponds to one port.
Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power
down. Corresponds to one port.
Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power
down. Corresponds to one port.
Analog circuit power ground.
Analog circuit power ground.
Analog circuit power supply.
PLL circuit power ground.
PLL circuit power ground.
PLL loop filter.
PLL circuit power supply.
Crystal oscillator (24.576MHz±100ppm). The optimum values for the 100kΩ
resistor and 20pF capacitor.
Crystal oscillator (24.576MHz±100ppm). The optimum values for the 100kΩ
resistor and 20pF capacitor.
Digital circuit power supply.
Reference resistance pin. Connect R1 and R0 with 6.8kΩ±5% resistor. R0
may be connected to ground.
Reference resistance pin. Connect R1 and R0 with 6.8kΩ±5% resistor. R0
may be connected to ground.
Analog circuit power ground.
XISO = LOW indicates isolation barrier which enables digital differentiator.
Analog circuit power ground.
Analog circuit power ground.
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CXD1944R
Name
Physical-ID
R
CPS
RHB
IBR
Size
6
1
1
1
1
GC
SPD
NP
ASTAT(n)
6
2
4
2
BSTAT(n)
2
Ch(n)
Con(n)
P(n) Fast
LoopInt
1
1
1
1
CPStatInt
CPStat
IDidIt
1
1
1
IllegalReq
ChipRev
Slow Pin
Slow Bit
ArbRstReq
Ping Timer
1
4
1
1
1
16
Type
R
R
R
R/W
R/W
R/W
R
R
R
R
R
R
R
R/W
R/W
R
R
R
R
R
R/W
R/W
R
Description
The address number of this node. Determined during Self-ID.
Indicates that this node is the root.
Cable power status.
Root Holding Bit. Attempts to become the root during next bus reset if set to “1”.
Initiate Bus Reset. Generates bus reset when possible after being set to “1”.
Cleared after bus reset.
Gap Count. Used to optimize gap time according to bus scale.
Indicates this node’s highest speed; 200Mbps when “01”, 100Mbps when “00”.
Indicates the number of ports on this node.
Indicates port n TPA status.
11 = Z, 01 = 1, 10 = 0, 00 = invalid
Indicates port n TPB status.
11 = Z, 01 = 1, 10 = 0, 00 = invalid
When the value is “1”, indicates that port n is the Child. “0” indicates Parent.
When the value is “1”, indicates that the active cable is connected to port n.
When the value is “1”, indicates that port n supports 200Mbps.
This is set to “1” when Tree-ID is not completed in time, which means that the
bus may be forming a loop.
Indicates a drop in cable power line voltage.
Same as CPS.
Indicates that this node generates the last bus reset. More than one node
may set this value.
Indicates an illegal LReq is detected.
Indicates the chip revision number.
Indicates XSLOW pin is set to LOW.
When set to “1”, the node acts as a 100Mbps PHY. Default is “0”.
Initiate the arbitrated bus reset. Cleared after bus reset.
50MHz Ping Timer count. A count starts when a configuration packet is trans-
mitted and stops when the first packet is received. The value may not be cleared
until the next configuration packet is sent.
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