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PDF CY2CC1810 Data sheet ( Hoja de datos )
| Número de pieza | CY2CC1810 | |
| Descripción | 1:10 Clock Fanout Buffer with Output Enable | |
| Fabricantes | Cypress Semiconductor | |
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( DataSheet : www.DataSheet4U.com )
COMLINK™ SERIES
CY2CC1810
1:10 Clock Fanout Buffer with Output Enable
Features
• Low-voltage operation
• VDD range from 2.5 to 3.3V
• 1:10 fanout
• Drives either a 50-ohm or 75-ohm transmission line
• Over voltage tolerant input hot swappable
• Low input capacitance
• Low output skew
• Low propagation delay
• Typical (tpd < 4 ns)
• High-speed operation > 200 MHz
• LVTTL-/LVCMOS-compatible input
— Output disable to three-state
• Industrial versions available
• Packages available include: SOIC/SSOP
Block Diagram
Description
The Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1810 fanout buffer features one input and
ten three-state outputs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance-matching and eliminate the need for
series-damping resistors; they also reduce noise overall.
Pin Configuration
OE#
VDD
IN
GND
Pin Description
Pin Number
1,7,8,12,13,17,20,24
3,10,15,22
5
6
2,4,9,11,14,16,18,19,21,23
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
OUTPUT (AVCMOS)
Pin Name
GND
VDD
OE#
IN
Q10........Q1
GND
Q10
VDD
Q9
OE#
IN
GND
GND
Q8
VDD
Q7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 GND
23 Q1
22 VDD
21 Q2
20 GND
19 Q3
18 Q4
17 GND
16 Q5
15 VDD
14 Q6
13 GND
24 pin SOIC/SSOP
Pin Description
Ground
Power
Power Supply
Power
Output Enable
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Output
AVCMOS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07055 Rev. *A
Revised May 7, 2002
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1 page  
COMLINK™ SERIES
CY2CC1810
Parameter Measurement Information: VDD @ 3.3V [9,11,12]
From Output
Under Test
CL = 50 pF
500 ohm
500 ohm
2x VDD
Open
VSS
Figure 6. Load Circuit
Input
Input
tw(50-50)
2.7 V
1.5 V
1.5 V
0V
tw(20-80)
2.7 V
1.5 V
0V
Figure 7. Voltage Waveforms–Pulse Duration
From Output
Under Test
CL = 3 pF
500 ohm
Figure 8. Point-to-Point Load Circuit
Input
1.5 V
1.5 V
1.5 V
0V
Output
tPLH
tPHL
1.5 V
1.5 VVOH
VOL
Figure 9. Voltage Waveforms–
Propagation Delay Times[15]
Output Control
(low-level enabling)
VOH (min)
1.5 V
3.3 V
VOL
(max)
0V
tPZL
Waveform 1 Z
S1 at 2 x VDD
tPZH
Waveform 2
S1 at GND Z
1.5 V
1.5V
tPLZ
3V
VOL + 0.3V VOL
tPHZ
VOH- 0.3V VOH
~0 V
Table 2.
Figure 10. Voltage Waveforms–
Enable and Disable Times[10,13,14]
Test
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2xVDD
VSS
See Figure 9
See Figure 10
INPUT
OUTPUT
tPLH
3V
1.5V
0V
tPHL
VOH
1.5V
VOL
l ltsk(P) = tPHL - tPLH
Figure 11. Pulse Skew–tsk(p)
Notes:
9. CL includes probe and jig capacitance
10. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH, except when disabled by the output control.
11. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50Ω, tR < 2.5 nS, tF < 2.5 nS.
12. The outputs are measured one at a time with one transition per measurement.
13. tPLZ and tPHZ are the same as tDIS.
14. tPZL and tPZH are the same as tEN.
15. tPLH and tPHL are the same as tPD.
Document #: 38-07055 Rev. *A
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| PDF Descargar | [ Datasheet CY2CC1810.PDF ] | |
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