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PDF PSB2197 Data sheet ( Hoja de datos )
| Número de pieza | PSB2197 | |
| Descripción | Subscriber Access Controller For Upn-interface Terminals | |
| Fabricantes | Infineon Technologies Corporation | |
| Logotipo |  |
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ICs for Communications
ISDN Subscriber Access Controller
for Upn-Interface Terminals
SmartLink-P
PSB 2197
User’s Manual 02.95
1 page  
General Information
Introduction
The PSB 2197, SmartLink-P, implements the subscriber access functions for a digital
terminal to be connected to a two-wire Upn-interface.
The PSB 2197 SmartLink-P is an optimized device for TE-applications, covering the
complete layer-1 and basic layer-2 functions for digital terminals.
The PSB 2197 SmartLink-P combines the functions of the Upn-transceiver with reduced
loop length (one channel of the OCTAT®-P PEB 2096) and a simple HDLC-controller for
signaling data onto one chip.
A pulse width modulator is included to provide an LCD-contrast control or a ring tone
signal.
The serial control port of the SmartLink-P is compatible to most serial interfaces of
microcontrollers. In addition it provides the microcontroller clock signal as well as an
undervoltage detector and reset generation including a watchdog function.
The Terminal Repeater function of the SmartLink-P allows to cascade two telephones
which are controlled by one Upn-interface from the line card or to extend the loop length
by using an IEC-Q transceiver.
The SmartLink-P can also be used as a simple HDLC-controller which provides the
TIC-bus access procedure. In this mode, the Upn-transceiver is inactive.
The PSB 2197 SmartLink-P interfaces to voice/data devices via the IOM®-2 interface
and provides an additional bit clock and strobe signal for standard codecs. The upstream
B-channel information may be muted or loop back the downstream data.
The PSB 2197 SmartLink-P is a 1-micron CMOS device offered in a P-DSO-28 package.
It operates from a single 5-V supply.
Note: Upn in the document refers to a version of the Up0-standard with a reduced loop
length.
Semiconductor Group
5
5 Page 
Features
Pin Definitions and Functions (cont’d)
Pin TE-Mode TR-Mode
HDLC-
No. Controller
Mode
P-DSO-28 Symbol
Input (I)
Output (O)
Open Drain
(OD)
Symbol
Input (I)
Output (O)
Open Drain
(OD)
Symbol
Input (I)
Output (O)
Open Drain
(OD)
Function
5 Lla I/O Lla I/O Lla I/O Line Interface a.
6 Llb I/O Llb I/O Llb I/O Line Interface b.
Upn-transceiver
signals. In
HDCL-controller mode
both pins must be
connected via a 10 kΩ
resistor.
27 BCL O
0, low O
BCL O
Bit Clock.
IOM-bit clock signal
(768 kHz) in TE- and
HDLC-controller mode
if programmed by
SDS-bits. In TR-mode,
the default value of
CTRL4 fixes BCL to ‘0’.
28 SDS O
0, low O
SDS
O
Serial Data Strobe.
Strobe signal to
indicate 64 kbit/s
time-slot in TE- and
HDLC-mode. In
TR-mode, the default
value of CTRL4 fixes
SDS to ‘0’.
1 PWO/ O
RING
HDLC/ I
TR
HDLC/ I
TR
Pulse Width
Output/Ring/Mode.
Provides the output of
the pulse width
modulator or ring tone
generator.
Selects between
HDLC-(1) and TR-(0)
mode if TR/TE = 1.
Semiconductor Group
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PSB2197.PDF ] | |
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