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PDF STMP3505 Data sheet ( Hoja de datos )
| Número de pieza | STMP3505 | |
| Descripción | D-Major Audio System on Chip | |
| Fabricantes | SigmaTel | |
| Logotipo |  |
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Integrated Mixed-Signal Solutions
PRODUCT DATA SHEET
STMP35xx
D-Major™Audio System on Chip
with USB 2.0, LCD, Voice Record and Battery Charger
Third Generation Audio Decoder
Version 1.07 November 9, 2004
90
94
FM Tuner
98 102 106
Host Processor
(Optional)
Rechargeable
Battery
Hi-Speed USB
LED/LCD Screen
SDRAM
Microphone
Voice Record
Flash Memory
Hard Drive
Buttons/Switches CD Pickup
Headphones
OFFICIAL PRODUCT DOCUMENTATION 12/1/04
5-35xx-D1-1.07-110904
Copyright © 2004 SigmaTel, Inc.
All rights reserved.
SigmaTel, Inc. makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document,
and makes no commitment to update the information contained herein. SigmaTel reserves the right to change or discontinue this product at
any time, without notice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on
information in this document.
The following are trademarks of SigmaTel, Inc., and may be used to identify SigmaTel products only: SigmaTel, the SigmaTel Logo, C Major,
D Major and Go-Chip. Other products and company names contained herein may be trademarks of their respective owners.
1 page  
OFFICIAL PRODUCT DOCUMENTATION 12/1/04
STMP35xx
D-Major™Audio System on Chip
2.3.
Description
SigmaTel's STMP35xx is a third generation single-chip highly-integrated digital music
system solution for devices such as digital audio players, PDAs, voice recorders, MP3-
encode recorders, and cell phones. It includes a high performance DSP, 288KBytes of
on-chip SRAM, and a USB 2.0 interface (including High speed 480Mb/second transfers)
for downloading music and uploading voice and MP3 recordings. The chip also includes
a mixer, DAC, ADC and provides interfaces to IDE Hard Drives, CD-DSPs, Flash mem-
ory, LCD/LEDs, button & switch inputs, headphone driver, FM tuner input & controls and
a microphone. The chip’s highly programmable architecture supports MP3, WMA, and
other digital audio standards. WMA digital rights management and other security
schemes are also supported. For devices like PDAs and cell phones, the STMP35xx
can act as a slave chip to a host chip/processor.
The DAC includes a headphone driver to directly drive low impedance headphones. The
ADC includes inputs for both microphone and analog audio in to support voice recording &
FM radio integration and MP3 encode features. SigmaTel's proprietary Sigma-Delta (Σ∆)
technology achieves a DAC SNR in excess of 90 dB for high-quality audio playback.
The STMP35xx has low power consumption to allow long battery life and includes an
efficient flexible on-chip DC-DC converter that allows many different battery configura-
tions, including 1xAA, 1xAAA, 2xAA, 2xAAA and LiIon. The chip includes an integrated
intelligent charger for NiMH and LiIon batteries. In addition, the single-chip design and
low pin count enables very small digital audio devices to be designed.
2.3.1.
DSP Core
The on-chip DSP core is modeled exactly after the Motorola DSP56004. It supports
the identical instruction set, registers, addressing modes, etc., as the DSP56000
family of digital signal processors. Figure 3 shows a high level view of the DSP core.
This architecture is highly optimized for battery operated audio applications. Its 24-
bit intrinsic data size provides sufficient precision for high quality audio algorithms
while minimizing the number of register and data path signals that must be toggled
for any operation. The term “WORD”, as used in this data sheet, refers to a 24-bit
unit of storage unless otherwise noted.
The functionality that defines the on-chip DSP, is the memory map, interrupt pro-
cessing, and peripherals it offers.
The integrated DSP comprises three execution units, an interrupt controller and a
debug interface. It connects to the rest of the STMP35xx chip via three memory bus-
ses, a set of interrupt input signals and various reset and clock inputs. It implements
a 3 memory space Harvard architecture, simultaneously referencing an X data ele-
ment, a Y data element and a program element. These references are conveyed
over the program or “P” bus, the X bus and the Y bus. Each bus comprises a 24 bit
wide data path and a 16 bit address bus. Program accessible I/O registers reside in
the top 4K word addresses on the X-bus. The DSP architecture has special pro-
grammed I/O support for the top 64 words of this space but SigmaTel has extended
this space to the top 4K words, i.e. addresses $F000 through $FFFF, inclusive.
The DSP Core also implements the OnCE debugger that is the norm for this DSP
architecture. The OnCE interface connects to an external debugger over four I/O
signal pins on the STMP35xx.
Using an industry standard instruction set architecture and debugger interface for
the integrated DSP means that development tools and debuggers are in the highly
evolved and stable portion of their life cycle. In addition, it means that system devel-
5-35xx-D1-1.07-110904
5
5 Page 
OFFICIAL PRODUCT DOCUMENTATION 12/1/04
STMP35xx
D-Major™Audio System on Chip
leakage currents. For LiIon mode, the I/O Vdd rail is connected to ground instead of
connecting to BATT.
In addition to the various voltage detectors, a power up or power down event can be
signaled by the special power switch circuitry in the DC to DC converters. A simple
resistor network and momentary contact push button switch is sufficient for player
on/off control.
There is a special three channel low resolution A/D converter on-chip to help with
battery based applications. One channel is dedicated to measuring the voltage on
the BATT pin and is used to monitor the battery condition to estimate its remaining
life. All low resolution channel also have digital trip point comparator functions that
can be used to generate interrupts to the DSP. The trip point can be programmati-
cally set at one of 512 levels for battery brown out detection on the Battery LRADC
or for threshold detection on the other two LRADCs. NOTE: ONLY the battery can
be connected directly to the BATT pin for correct operation of the device, thus the
battery channel of the low resolution A/D converter is not available for any other pur-
pose. The second and third low resolution A/D converters are uncommitted and
available for application use. An optional current source can be enabled to either the
second or third LRADC pin to support external temperature sensors with minimal
external components.
In addition, the DC to DC converters have comparators to monitor their output volt-
ages. They can report “brownout” conditions resulting from over drawing their power
capabilities. These conditions are reported either on a normal interrupt level or as a
non-maskable interrupt (NMI).
The device contains an integrated PLL which is referenced to the 24.0MHz crystal
oscillator. It can generate clock sources from 39.6MHz to 120.0MHz in steps of
1.2MHz. It includes a post divide stage for the digital clock from a divide by one to a
divide by 2048. With the PLL turned off and the post divider set to 2048, one can
achieve a low power 11.7KHz operating point.
POWER SOURCE
1 Alkaline or 1 NiMH
(0.9V-1.5V)
1 Alkaline or 1 NiMH
(0.9V-1.5V)
LiIon, (3.0-3.6V)
2 Alkaline or 2 NiMH
(1.8V-3.0V)
LiIon (3.3V-4.2V)
VDD I/O
DCDC1
DCDC_VddIO
Boost
3.3V
VDD D
DCDC1
DCDC_VddD
Boost
1.8V
DCDC1
DCDC1
DCDC_VddIO
DCDC_VddD
Boost
Boost
3.3V
1.8V
lowest cost (shared
passives & 100-pin)
LiIon Battery
DCDC1
Buck
1.8V
DCDC2
DCDC1
Boost
Buck
3.3V
1.8v
DCDC2
DCDC1
Buck
Buck
3.3V
1.8V
Table 1. Flexible Battery Configurations
VDD A
DCDC1
DCDC_VddA
Boost
1.8V
better noise floor
(144-pin)
DCDC1
DCDC_VddD
Boost
1.8V
DCDC1
Buck
1.8V
DCDC1
Buck
1.8V
DCDC1
Buck
1.8V
5-35xx-D1-1.07-110904
11
11 Page | ||
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| PDF Descargar | [ Datasheet STMP3505.PDF ] | |
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