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PDF TS358 Data sheet ( Hoja de datos )

Número de pieza TS358
Descripción Dual Operating Amplifier
Fabricantes Taiwan Semiconductor Company 
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TS358
Dual Differential Input Operational Amplifiers
Low power drain
operational amplifier
DIP-8
SOP-8
General Description
Utilizing the circuit designs perfected for recently introduced Quad Operational Amplifiers, these
dual operational amplifiers feature 1) low power drain, 2) a common mode input voltage range
extending to ground/VEE, 3) Single Supply or Split Supply operation, and 4) pin outs compatible with
the popular MC1558 dual operational amplifier.
These amplifiers have several distinct advantages over standard operational amplifier types in single
supply applications . They can operate at supply voltages as low as 3.0 Volts or as high as 32 Volts
with quiescent currents about one fifth of those associated with the LM741 (on a pet amplifier basis).
The common mode input range includes the negative supply, thereby eliminating the necessity for
external biasing components in many applications.
The output voltage range also includes the negative power supply voltage.
Features
Short circuit protected outputs
True differential input stage
Single supply operation : 3.0 V to 32 Volts
Low input bias currents
Pin Configuration
DIP-8
SOP-8
85
85
Internally compensated
Common mode range extends to negative
supply
Single and split supply operation
Similar performance to the popular MC1558
Ordering Information
DEVICE
TS358CD
TS358CS
OPERATING TEMPERATURE
(Ambient)
-20 to +85+
PACKAGE
DIP-8
SOP-8
14
14
PIN : 1. Output A
2. Input A
3. Input A
4. VEE /Gnd
5. Input B
6. Input B
7. Output B
8. VCC
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TS358 pdf
REPRESENTATIVE CIRCUIT SCHEMATIC
Q16
Q19
5.0 pF
Q15
Q14
Q13
40k
Q12
25
Output
Bias Circuitry
Common to Both
Amplifiers
VCC
Q22
Q24
Q23
Inputs
Q18
Q17
Q2
Q3
Q20
Q21
Q5
Q4
Q6 Q7
Q8
Q26
Q9
Q11
Q10
Q25
Q1 2.4k
2.0k
VEE /Gnd
CIRCUIT DESCRIPTION
The TS358 series made using two internally compensated,two-stage operational amplifiers.
The first stage of each consists of differential input devices Q20 and Q18 with input buffer
transistors Q21 and Q17 and differential to single ended converter Q3 and Q4. The first stage
performs not only the first stage gain function but also performs the level shifting and
transconductance reduction functions. By reducing the transconductance, a smaller compen-
sation capacitor (only 5.0pF) can be empllyed, thus saving chip area. The transconductance
reduction is accomplished by splitting the collectors of Q20 and Q18. Another feature of this
input stage is that the input common mode range can include the negative supply or ground, in
single supply operation, without saturating either the input devices or the differential to single-
ended converter. The second stage consists of a standard current source load amplifier stage.
Each amplifier is biased from an internal-voltage regulator which has a low temperature coeffi-
cient thus giving each amplifier good temperature chatacteristics as well as excellent power
supply rejection.

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