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PDF HY27UF084G2M Data sheet ( Hoja de datos )
| Número de pieza | HY27UF084G2M | |
| Descripción | 4Gbit (512K x 8-Bit) NAND Flash | |
| Fabricantes | Hynix Semiconductor | |
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Preliminary
HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
4Gb NAND FLASH
HY27UF084G2M
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.3/ Nov. 2005
1
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1 page  
Preliminary
HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UF084G2M series is a 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 4096 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP# input pin or using the extended lock block feature described later.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-
tiple memories the RB# pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UF084G2M extended reliability of 100K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the
code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-
tion.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,
Read ID2 extension.
The HYNIX HY27UF084G2M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27UF084G2M
ORIZATION
x8
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1 / 52-ULGA
Rev. 0.3 / Nov. 2005
5
5 Page 
Preliminary
HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
CLE
ALE
CE#
WE#
RE#
WP#
MODE
H
L
L
H
L Rising H
L Rising H
X
X
Read Mode
Command Input
Address Input(5 cycles)
H
L
L
H
L Rising H
L Rising H
H
H
Write Mode
Command Input
Address Input(5 cycles)
L L L Rising H H Data Input
L L L(1) H Falling X Sequential Read and Data Output
L L L H H X During Read (Busy)
X X X X X H During Program (Busy)
X X X X X H During Erase (Busy)
X X X X X L Write Protect
X X H X X 0V/Vcc Stand By
Table 6: Mode Selection
NOTE:
1. With the CE# don’t care option CE# high during latency time does not stop the read operation
Rev. 0.3 / Nov. 2005
11
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