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PDF SPCA500A Data sheet ( Hoja de datos )
| Número de pieza | SPCA500A | |
| Descripción | Digital Camera Chipset | |
| Fabricantes | Sunplus | |
| Logotipo |  |
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1 page  
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SPCA500A
Digital Camera Chipset
The serial programming sequence for the CDS/AGC/ADC interface is as follows. First, users set data
to PRG_MODE and CDSBITS as the programming mode, then users write serial data bytes into
CDS_REG1, CDS_REG2 through CDS_REGA. Every writing of CDS_REGA will schedule a serial
data transfer at the next frame start. Bits that exceed the number of CDSBITS will be discarded. Each
data byte is shifted out in MSB-first manner. Several serial interfaces are defined as follows :
PRG_MODE=0
PRG_MODE=1
PRG_MODE=2
PRG_MODE=3
Only SCK, SDATA, no SLOAD signal needed. One dummy SCK pulse cycle to
lead actual data. Every rising SCK to latch SDATA. The falling edge of SCK
which latches SDATA at high denotes the end of transfer. (eg. SHARP IR3Y38M)
Three signals are used. SCK starts to fall after SLOAD is low. Every rising SCK
to latch SDATA. (eg. Hitachi HD49322BF)
Three signals are used. SCK starts to rise after SLOAD is low. Every rising SCK
to latch SDATA. (eg. ADI AD9803, EXAR XRD44L61)
Three signals are used. Every rising SCK to latch SDATA. SLOAD stays low
during SCK is clocking, then one pulse of SLOAD denotes the end of transfer. (eg.
Panasonic AN2104FHQ)
1999/10/05 Ver. 0.2
5
Preliminary
5 Page 
z~0]¶ûù
SPCA500A
Digital Camera Chipset
If the DRAM is used as the storage element, the DRAM must enters self-refresh state when the camera
is not in operation. This will save a lot of power. A register bit in the DRAM controller register set is
dedicated to this function. To save image into the DRAM or unload the images from the DRAM, the
micro-controller must set a set of range registers. They define the starting address and ending address
of the saving/unloading area. The data is stored into (or read from) the DRAM in raster-scan order.
Note that the DRAM controller restricts the DRAM range to be set based on a 4-words block. Only
4*N (the multiples of 4) are legal for the starting column address. And only 4N+3 is legal for the
ending column address.
3.6. Embedded Micro Controller
The SPCA500A has integrated an 8032-compatible micro-controller, a serial communication port and
a build-in 4Kx 8 SRAM. To simplify the firmware development, the users may disable the internal
micro-controller and connect the SPCA500A to an external micro-controller.
Internal CPU connection
romwr
cs0nn
a16
psenn
ale
cpuad[7:0]
cpua[15:8]
romwr
cs0nn
a16
psen
ale
cpuad[7:0]
cpua[15:8]
latch
128K FLASH ROM
PPC CHIP
gpio_0
gpio_1
gpio_2
gpio_3
gpio_5
gpio_6
gpio_7
augpio_1
augpio_4
augpio_6
augpio_7
p3_0
p3_1
p3_3
flashlight
igbt_on
gpio1
gpio2
di
do
pclk
pwr1
request
pwr2
pwr3
rxd
txd
int1nn
(from SPL15A)
(to SPL15A)
(from SPL15A)
(to SPL15A)
For internal 8051 connection, the cpu read/write signals are not routed out of the 128-pin package.
If using external SRAM, the shadow function for ISP is not supported.
wrnn
rdnn
cs0nn
a16
psenn
ale
cpuad[7:0]
cpua[15:8]
External CPU connection
latch
32K SRAM
128K FLASH ROM
gpio_0 rom_wr_enn
gpio_1 shadow_on
PPC chip
gpio_5
gpio_6
gpio_7
augpio_4
di
do
pclk
request
(from SPL15A)
(to SPL15A)
(from SPL15A)
(to SPL15A)
External 805p13 _ 0
p3_1
txd
rxd
wrnn
rdnn
cs0nn
a16
psen
ale
cpuad[7:0]
cpua[15:8]
p3_3
int1nn
int0nn
For external CPU connection, gpio_3 and gpio_2 are used as read/write inputs from the external 8051
1999/10/05 Ver. 0.2
11
Preliminary
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet SPCA500A.PDF ] | |
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