|
|
PDF MC33887 Data sheet ( Hoja de datos )
| Número de pieza | MC33887 | |
| Descripción | 5.0 A H-Bridge with Load Current Feedback | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MC33887 (archivo pdf) en la parte inferior de esta página. Total 32 Páginas | ||
|
No Preview Available !
Freescale Semiconductor
Technical Data
5.0 A H-Bridge with Load
Current Feedback
The 33887 is a monolithic H-Bridge Power IC with a load current
feedback feature making it ideal for closed-loop DC motor control.
The IC incorporates internal control logic, charge pump, gate drive,
and low RDS(ON) MOSFET output circuitry. The 33887 is able to
control inductive loads with continuous DC load currents up to 5.0 A,
and with peak current active limiting between 5.2 A and 7.8 A.
Output loads can be pulse width modulated (PWM-ed) at
frequencies up to 10 kHz. The load current feedback feature
provides a proportional (1/375th of the load current) constant-current
output suitable for monitoring by a microcontroller’s A/D input. This
feature facilitates the design of closed-loop torque/speed control as
well as open load detection.
A Fault Status output terminal reports undervoltage, short circuit,
and overtemperature conditions. Two independent inputs provide
polarity control of two half-bridge totem-pole outputs. Two disable
inputs force the H-Bridge outputs to tri-state (exhibit high
impedance).
The 33887 is parametrically specified over a temperature range
of -40°C ≤ TA ≤ 125°C and a voltage range of 5.0 V ≤ V+ ≤ 28 V. The
IC can also be operated up to 40 V with derating of the
specifications.
Features
• 5.0 V to 40 V Continuous Operation
• 120 mΩ RDS(ON) H-Bridge MOSFETs
• TTL/CMOS Compatible Inputs
• PWM Frequencies up to 10 kHz
• Active Current Limiting (Regulation)
• Output Short Circuit Protection (Short to V+ or Short to GND)
• Undervoltage Shutdown
• Fault Status Reporting
• Sleep Mode with Current Draw ≤50 µA (Inputs Floating or Set
to Match Default Logic States)
• Pb-Free Packaging Designated by Suffix Codes VW and PNB.
MC33887
Rev 10.0, 07/2005
33887
5.0 A H-BRIDGE
DH SUFFIX
VW (Pb-FREE) SUFFIX
98ASH70273A
20-TERMINAL HSOP
PNB (Pb-FREE) SUFFIX
98ASA10583D
36-TERMINAL PQFN
Bottom View
DWB SUFFIX
98ASA10506D
54-TERMINAL SOICW-EP
ORDERING INFORMATION
Device
MC33887DH/R2
PC33887VW/R2
MC33887PNB/R2
Temperature
Range (TA)
-40°C to 125°C
Package
20 HSOP
36 PQFN
MC33887DWB/R2
54 SOICW-EP
5.0 V
33887
V+
CCP V+
IN
OUT
MCU
OUT
OUT
OUT
OUT
A/D
OUT1
FS
MOTOR
EN
IN1 OUT2
IN2
D1 PGND
D2
FB AGND
Figure 1. 33887 Simplified Application Diagram
There are no disclaimers required on the Final publication of a data sheet.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
www.DataSheet4U.com
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
TERMINAL CONNECTIONS
Transparent Top View of Package
PGND
PGND
PGND
PGND
NC
NC
NC
D2
NC
OUT2
OUT2
OUT2
OUT2
NC
V+
V+
V+
V+
NC
NC
NC
NC
CCP
D1
IN2
EN
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 PGND
53 PGND
52 PGND
51 PGND
50 NC
49 NC
48 NC
47 FB
46 NC
45 OUT1
44 OUT1
43 OUT1
42 OUT1
41 NC
40 V+
39 V+
38 V+
37 V+
36 NC
.35 NC
34 NC
33 NC
32 IN1
31 FS
30 AGND
29 NC
28 NC
Figure 5. 33887 Terminal Connections
Table 3. SOICW-EP TERMINAL DEFINITIONS
A functional description of each terminal can be found in the Functional Terminal Description section, page 20.
Terminal
1–4, 51–54
5–7, 9, 14, 19–22,
27– 29, 33–36, 41,
46, 48–50
8
Terminal
Name
PGND
NC
D2
Formal Name
Power Ground
No Connect
Disable 2
Definition
High-current power ground.
No internal connection to this terminal.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
10 – 13
15 –18, 37–40
23
OUT2
V+
CCP
H-Bridge Output 2
Positive Power Supply
Charge Pump Capacitor
Output 2 of H-Bridge.
Positive supply connections.
External reservoir capacitor connection for internal charge pump
capacitor.
24 D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
25
IN2
Logic Input Control 2
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
26 EN
Enable
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
30
AGND
Analog Ground
Low-current analog signal ground.
31 FS Fault Status for H-Bridge Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33887
5
5 Page 
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
TIMING CHARACTERISTICS
PWM Frequency (23)
Maximum Switching Frequency During Active Current Limiting (24)
Output ON Delay (25)
V+ = 14 V
fPWM – 10 – kHz
fMAX – – 20 kHz
t D (ON)
–
µs
– 18
Output OFF Delay (25)
V+ = 14 V
t D (OFF)
–
µs
– 18
ILIM Output Constant-OFF Time for Low-Side MOSFETs (26), (27)
ILIM Blanking Time for Low-Side MOSFETs (28), (27)
Output Rise and Fall Time (29)
V+ = 14 V, IOUT = 3.0 A
tA
tB
tF, tR
15 20.5 26 µs
12 16.5 21 µs
µs
2.0 5.0 8.0
Disable Delay Time (30)
Power-ON Delay Time (31)
Wake-Up Delay Time (31)
Output MOSFET Body Diode Reverse Recovery Time (32)
t D (DISABLE)
–
– 8.0 µs
t POD
– 1.0 5.0 ms
t WUD
tRR
– 1.0
100 –
5.0 ms
– ns
Notes
23. The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM
pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching
frequency. See Typical Switching Waveforms, Figures 12 through 19, pp. 14–16.
24. The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces
a constant-OFF-time pulse-width modulation of the output current. The output load’s inductance, capacitance, and resistance
characteristics affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit.
25. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to
the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal
to the 10% point of the output response signal. See Figure 6, page 12.
26. ILIM Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated
the output bridge.
27. Load currents ramping up to the current regulation threshold become limited at the ILIM value. The short circuit currents possess a di/dt
that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and causing the
shutdown circuitry to force the output into an immediate tri-state latch-OFF. See Figures 10 and 11, page 13. Operation in Current Limit
mode may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to
progressively “fold back”, or decrease with temperature, until ~175°C is reached, after which the TLIM thermal latch-OFF will occur.
Permissible operation within this fold-back region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See
Figure 9, page 12.
28. ILIM Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold
comparators my have time to act.
29. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 8, page 12.
30. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
Figure 7, page 12.
31. Parameter has been characterized but not production tested.
32. Parameter is guaranteed by design but not production tested.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33887
11
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet MC33887.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MC33880 | CONFIGURABLE OCTAL SERIAL SWITCH WITH SERIAL PERIPHERAL INTERFACE | Motorola Semiconductors |
| MC33882 | Six-Output Low-Side Switch with SPI and Parallel Input Control | Motorola Semiconductors |
| MC33883 | H-Bridge Gate Driver IC | Motorola Semiconductors |
| MC33884 | SWITCH MONITOR INTERFACE | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |