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PDF SH66P20A Data sheet ( Hoja de datos )
| Número de pieza | SH66P20A | |
| Descripción | OTP 4-Bit Microcontroller | |
| Fabricantes | Sino Wealth Microelectronic | |
| Logotipo |  |
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SH66P20A
OTP 4-bit Microcontroller
Features
SH6610C-based single-chip 4-bit microcontroller
ROM: 1K X 16 bits
RAM: 64 X 4 bits (Data memory)
Operation voltage: 2.4V - 6.0V (Typical 3.0V or 5.0V)
12 CMOS bi-directional I/O pins
4-level subroutine nesting (including interrupts)
One 8-bit auto re-load timer/counter
Warm-up timer for power on reset
Powerful interrupt sources:
- Internal interrupt (Timer0)
- External interrupts: PortB & PortC (Falling edge)
Oscillator (user option)
- X`tal oscillator:
32.768KHz ~ 4MHz
- Ceramic resonator: 400K ~ 4MHz
- RC oscillator:
400K ~ 4MHz
- External clock:30K ~ 4MHz
Instruction cycle time:
- 4/32.768KHz (≈ 122us) for 32.768KHz OSC clock
- 4/4MHz (= 1us) for 4MHz OSC clock
Two low power operation modes: HALT and STOP
OTP type
Code protection
Built-in watchdog timer
General Description
SH66P20A is a 4-bit microcontroller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 1K program ROM, Timer
and I/O Port.
Pin Configuration
PORTA.2
PORTA.3
T0
RESET
GND
PORTB.0
PORTB.1
PORTB.2
PORTB.3
1
2
3
4
5
6
7
8
9
18 PORTA.1
17 PORTA.0
16 OSCI
15 OSCO
14 VDD
13 PORTC.3
12 PORTC.2
11 PORTC.1
10 PORTC.0
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1 V2.3
1 page  
SH66P20A
4. Low Power Detection (LPD)
The LPD function is to monitor the supply voltage and applies an internal reset in the microcontroller at the time of battery
replacement. If the applied circuit satisfies the following conditions, the LPD can be incorporated by software control.
- High reliability is not required
- Power supply voltage VDD = 2.4V to 6.0 V
- Operating ambient temperature TA = -20℃ to + 70℃
4.1. Functions of LPD Circuit
The LPD circuit has the following functions:
- Generates an internal reset signal when VDD ≤ VLPD
- Cancels the internal reset signal when VDD > VLPD
Here, VDD: power supply voltage, VLPD: LPD detect voltage, it is about 1.9 ± 0.3V
4.2. LPD Control Register
The LPD circuit is controlled by software enable flag
Address Bit3
Bit2
Bit1
Bit0 R/W
Remark
$07
LPD3 LPD2
LPD1
LPD0
W
LPD Enable Control (LPD3 ~ 0):
1010: LPD Enable (Default);
0101: LPD Disable
LPD3
1
0
LPD2
0
1
LPD1
1
0
LPD0
0
1
LPD Enable/Disable flag.
Enable LPD circuit (Power-on initial).
Disable LPD circuit.
5
5 Page 
SH66P20A
7.2. Timer0 Interrupt
The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt
enable flag is enabled, then a timer interrupt service routine will proceed. This can also be used to wake CPU from HALT mode.
7.3. Timer0 mode register
The timer can be programmed in several different prescaler ratio by setting Timer Mode register (TM0). The 8-bit counter counts
prescaler overflow output pulses. The timer mode registers (TM0) are 3-bit registers used for timer control as shown in table1.
These mode registers select the input pulse sources into the timer.
Timer 0 Mode Register ($02)
TM0.2
0
0
0
0
1
1
1
1
TM0.1
0
0
1
1
0
0
1
1
TM0.0
0
1
0
1
0
1
0
1
Prescaler Divide Ratio
/211
/29
/27
/25
/23
/22
/21
/20
Ratio N
2048 (initial)
512
128
32
8
4
2
1
7.4. External Clock/Event T0 as TMR0 Source
When external clock/event input is used for TM0, it is synchronized with CPU system clock. Therefore the external source must
follow certain constrains. The output from T0M multiplex is T0C. It is sampled by system clock in instruction frame cycle.
Therefore it is necessary for T0C to be high at least 2 tOSC and low at least 2 tOSC. When prescaler ratio selects /20, T0C is the
same as the system clock input. Therefore the requirement is as follows:
T0H = T0CH = T0 high time ≥ 2 tosc + ∆T
T0L = T0CL = T0 low time ≥ 2 tosc + ∆T
When other prescaler ratio is selected, the TM0 is scaled by the asynchronous ripple counter and so the prescaler output is
symmetrical.
Then:
T0C high time = T0C low time =
N* T0
2
Where
T0 = Timer0 input period
N = prescaler value
The requirement is, therefore:
N* T0
2
≥ 2 tosc + ∆T , or T0 ≥
4 * tOSC + 2 T
N
The limitation is applied for T0 period time only. The pulse width is not limited by this equation. It is summarized as follows:
T0 = Timer0 period ≥
4 * tOSC + 2 T
N
11
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| PDF Descargar | [ Datasheet SH66P20A.PDF ] | |
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