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PDF TM50S116T Data sheet ( Hoja de datos )

Número de pieza TM50S116T
Descripción SDRAM
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! TM50S116T Hoja de datos, Descripción, Manual

TMC
TM50S116T SDRAM
Description
The TM50S116T is organized as 2-bank x 524288-word x 16-bit(1Mx16),
fabricated with high performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
Features
n Package 400-mil 50-pin TSOP(II)
n JEDEC PC133/PC100 compatible
n Single 3.3V Power Supply
n LVTTL Signal Compatible
n Programmable
- CAS Latency (3 or 2 clocks)
- Burst Length (1,2,4,8 & full page)
- Burst type (Sequential & Interleave)
n
n
n Auto and Self Refresh
n 64ms refresh period (4K cycles)
n organization
n
n Pin33 and 37 are “No Connected”
n Fully synchronous operation referenced
to clock rising edge
Frequency vs. AC Parameter
Symbol
Parameter
tCK Min. clock cycle time @CL=3
fCK Max. operating frequency @CL=3
tAC Max. access time from CLK @CL=3
trcd Min. row to column delay
- 6 - 7 - 75 Unit
6 7 7.5 ns
166.7 143 133.3 Mhz
5.0 5.4 5.4 ns
18 18 20 ns
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1
TMC Rev:1.0

1 page




TM50S116T pdf
TMC
TM50S116T SDRAM
AC Characteristics
Recommended operating conditions(Vdd=VddQ=3.3V,Vss=0V,TA= 0 to 70 )
Symbol
Parameter
-6 -7 -75 Unit
1 tCK Clock Cycle Time,CL=3
2 fCK Clock Frequency,CL=3
3 tAC Clock Access Time,CL=3
4 tCH Clock High Pulse Width
5 tCL Clock Low Pulse Width
6 tIS Input Setup time(all inputs)
7 tIH Input Hold time(all inputs)
8 tT Transition time of clock
9 tRCD /RAS to /CAS delay
10 tRC Row Cycle time
11 tRAS Row active time
12 tRP Pre-charge time
13 tRRD Row active to active delay
14 tREF Refresh time
Min Max Min Max
6.0 7.0
166.7
143
5.0 5.4
2.5 2.5
2.5 2.5
1.5 1.5
0.8 0.8
1.0 10 1.0 10
18 18
60 63
42 42
15 18
12 14
64 64
Min Max
7.5
133.3
5.4
2.5
2.5
1.5
0.8
1.0 10
20
67
45
20
15
64
ns
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
For reference only.
5
TMC Rev:1.0

5 Page










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