PDF MT48LC8M16LFF4 Data sheet ( Hoja de datos )

Número de pieza	MT48LC8M16LFF4
Descripción	(MT48xx8Mxxxx) SYNCHRONOUS DRAM
Fabricantes	Micron Technology
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SYNCHRONOUS DRAM 128Mb: x16, x32 MOBILE SDRAM MT48LC8M16LFF4, MT48V8M16LFF4, MT48LC8M16TG, MT48V8M16TG, MT48V8M16P, MT48LC4M32LFF5, MT48V4M32LFF5 Features Table 1: Configurations • Temperature Compensated Self Refresh (TCSR) • Fully synchronous; all signals registered on positive 8 MEG X 16 4 MEG X 32 edge of system clock • Internal pipelined operation; column address can mbe changed every clock cycle • Internal banks for hiding row access/precharge o• Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT auto .cprecharge, and Auto Refresh Modes • Self Refresh Mode; standard and low power • 64ms, 4,096-cycle refresh U• LVTTL-compatible inputs and outputs • Low voltage power supply t4• Partial Array Self Refresh power-saving mode eOptions Marking • VDD/VDDQ e3.3V/3.3V h2.5V/2.5V – 1.8V • Configurations S8 Meg x 16 (2 Meg x 16 x 4 banks) 4 Meg x 32 (1 Meg x 32 x 4 banks) ta• Package/Ball out 54-ball VFBGA (8mm x 8mm)1 a54-ball VFBGA (8mm x 8mm)1 Lead-Free 90-ball VFBGA (8mm x 13mm)2 .D90-ball VFBGA (8mm x 13mm)2 Lead-Free 54-Pin TSOP II (400 mil) 54-Pin TSOP II (400 mil) Lead-Free w• Timing (Cycle Time) 7.5ns @ CL = 3 (133 MHz) w8ns @ CL = 3 (125 MHz) 10ns @ CL = 3 (100 MHz) m• Temperature w oCommercial (0°C to +70°C) .cIndustrial (-40°C to +85°C) UExtended (-25°C to +75°C) LC V 8M16 4M32 F4 B4 F5 B5 TG P -75M -8 -10 None IT XT et4NOTE: 1. x16 only. e2. x32 only. Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 2 Meg x 16 x 4 banks 4K 4K (A0–A11) 4 (BA0, BA1) 512 (A0–A8) 1 Meg x 32 x 4 banks 4K 4K (A0–A11) 4 (BA0, BA1) 256 (A0–A7) Table 2: Key Timing Parameters CL = CAS (READ) latency ACCESS TIME SPEED CLOCK GRADE FREQUENCY CL = 1 CL = 2 CL = 3 tRCD tRP -75M -8 -10 -75M -8 -10 -8 -10 133MHz 125 MHz 100 MHz 100MHz 100 MHz 83 MHz 50 MHz 40 MHz - – – - – – 19ns 22ns - – – 6 8ns 8ns – – 5.4 19ns 19ns 7ns 20ns 20ns 7ns 20ns 20ns - 19ns 19ns – 20ns 20ns – 20ns 20ns – 20ns 20ns – 20ns 20ns Part Number Example: MT48V8M16LFB5-8 w.DataSh09005aef8071a76b ww128Mbx16x32Mobile_1.fm - Rev. J 7/04 EN 1 ©2001 Micron Technology, Inc. All rights reserved. 1 page Figure 1: 90-Ball FBGA Pin Assignment (Top View) 123456789 A DQ26 DQ24 VSS B DQ28 VDDQ VSSQ C VSSQ DQ27 DQ25 D VSSQ DQ29 DQ30 E VDDQ DQ31 NC F VSS DQM3 A3 G A4 A5 A6 H A7 A8 NC J CLK CKE A9 K DQM1 NC NC L VDDQ DQ8 VSS M VSSQ DQ10 DQ9 N VSSQ DQ12 DQ14 P DQ11 VDDQ VSSQ R DQ13 DQ15 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC DQ16 VSSQ A2 DQM2 VDD A10 A0 A1 NC BA1 A11 BA0 CS# RAS# CAS# WE# DQM0 VDD DQ7 VSSQ DQ6 DQ5 VDDQ DQ1 DQ3 VDDQ VDDQ VSSQ DQ4 VDD DQ0 DQ2 128Mb: x16, x32 MOBILE SDRAM Figure 2: 54-Pin TSOP Pin Assignment (Top View) x16 VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 VDDQ DQ5 DQ6 VssQ DQ7 VDD DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 x16 54 Vss 53 DQ15 52 VssQ 51 DQ14 50 DQ13 49 VDDQ 48 DQ12 47 DQ11 46 VssQ 45 DQ10 44 DQ9 43 VDDQ 42 DQ8 41 Vss 40 NC 39 DQMH 38 CLK 37 CKE 36 NC 35 A11 34 A9 33 A8 32 A7 31 A6 30 A5 29 A4 28 Vss Note: The # symbol indicates signal is active LOW. Figure 3: 54-Ball FBGA and 54-Ball VFBGA Pin Assignment (Top View) 123456789 A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS# RAS# WE# G NC/A12 A11 A9 BA0 BA1 CS# H A8 A7 A6 A0 A1 A10 J VSS A5 A4 Top View (Ball Down) A3 A2 VDD 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. 5 Page 128Mb: x16, x32 MOBILE SDRAM Table 5: Pin Descriptions: 54-Pin TSOP (x16 Only) TSOP PIN NUMBER 38 SYMBOL CLK 37 CKE 19 CS# 16, 17, 18 15, 39 WE#, CAS#, RAS# DQML, DQMH 20, 21 BA0, BA1 23, 24, 25, 29, 30, 31, 32, 33, 34, 22, 35 A0–A5 A6-A11 2, 4, 5, 7, 8, 10, 11, 13, DQ0–DQ7 42, 49,45, 47, 48, 50, 51 DQ8-DQ15 TYPE Input Input Input Input Input Input Input I/O DESCRIPTION Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command being entered. Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. LDQM corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered same state when referenced as DQM. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command Address Inputs: A0–A11 are sampled during the ACTIVE command (row- address A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output: Data bus (x16 Only) 36, 40 3, 9, 43, 49 6, 12, 46, 52 1, 14, 27 28, 41, 54 NC VDDQ VSSQ VDD VSS – Supply Supply Supply Supply No Connect: These pins should be left unconnected. Pin 36 is a no connect for this part but may be used as A12 in future designs. DQ Power: Isolated DQ power on the die to improve noise immunity. DQ Ground: Isolated DQ power on the die to improve noise immunity. Power Supply: Voltage dependant on option. Ground. 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. 11 Page

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