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PDF MB81F641642D Data sheet ( Hoja de datos )
| Número de pieza | MB81F641642D | |
| Descripción | 4 x 1M x 16-Bit SDRAM | |
| Fabricantes | Fujitsu Microelectronics | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
AE4.1E
MEMORY
CMOS
4 × 1 M × 16 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F641642D-75/-102/-102L .comCMOS 4-Bank × 1,048,576-Word × 16 Bit
Synchronous Dynamic Random Access Memory
Us DESCRIPTION
t4The Fujitsu MB81F641642D is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 16-bit format. The MB81F641642D features a fully synchronous
eoperation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F641642D SDRAM is designed to
ereduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
hThe MB81F641642D is ideally suited for workstations, personal computers, laser printers, high resolution graphic
Sadapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
tas PRODUCT LINE & FEATURES
aParameter
.DCL - tRCD - tRP
Clock Frequency
wCL = 2
Burst Mode Cycle Time
wCL = 3
Access Time From
w omClock
CL = 2
CL = 3
.cOperating Current
UPower Down Mode Current (ICC2P)
t4Self Refresh Current (ICC6)
-75
3 - 3 - 3 clk min.
133 MHz max.
10 ns min.
7.5 ns min.
6 ns max.
6 ns max.
90 mA max.
1 mA max.
1 mA max.
MB81F641642D
-102/-102L
2 - 2 - 2 clk min.
100 MHz max.
10 ns min.
10 ns min.
6 ns max.
6 ns max.
85 mA max.
1 mA max.
1 mA max./ 500 µA max.
Reference Value
@66MHz(CL=2)
2 - 2 - 2 clk min.
66 MHz max.
15ns min.
10 ns min.
8 ns max.
6 ns max.
70 mA max.
1 mA max.
1 mA max.
hee• Single +3.3 V Supply ±0.3 V tolerance
taS• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
a• Four bank operation
.D• Burst read/write operation and burst
wwwread/single write operation capability
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 15.6 µs)
• CKE power down mode
• Output Enable and Input Data Mask
1 page  
MB81F641642D-75/-102/-102L Preliminary (AE4.1E)
s FUNCTIONAL TRUTH TABLE Note *1
COMMAND TRUTH TABLE Note *2, *3, and *4
Function
CKE
Notes Symbol
n-1 n
Device Deselect
*5 DESL H X
No Operation
*5 NOP H X
Burst Stop
BST H X
Read
*6 READ H X
Read with Auto-precharge *6 READA H X
Write
*6 WRIT H X
Write with Auto-precharge *6 WRITA H X
Bank Active
*7 ACTV H X
Precharge Single Bank
PRE H X
Precharge All Banks
PALL H X
Mode Register Set
*8, 9 MRS H X
A13,
CS RAS CAS WE A12
(BA)
A11
A10
(AP)
A9
HX XXX X X X
LH HHX X X X
LHHLX X X X
LH LHV X L X
LH LHV X H X
LH LLV X L X
LH LLV XHX
L L HHV V V V
LL HLV X L X
LL HLX XHX
LL LLL L LV
A8
to
A0
X
X
X
V
V
V
V
V
X
X
V
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
V = Valid, L = Logic Low, H = Logic High, X = either L or H.
All commands assumes no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of clock.
NOP and DESL commands have the same effect on the part. Unless spcifically noted, NOP will
represent both NOP and DESL command in later discriptions.
READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
Required after power up. Refer to POWER-UP INITIALIZATION in page 19.
MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
5
5 Page 
MB81F641642D-75/-102/-102L Preliminary (AE4.1E)
(Continued)
Current
State
Refreshing
CS RAS CAS WE
HXXX
L HHX
LHLX
L LHX
Mode
Register
Setting
LLLX
HXXX
L HHH
L HH L
LHLX
L LXX
Addr
X
X
X
X
X
X
X
X
X
X
Command
Function
DESL
NOP (Idle after tRC)
NOP/BST NOP (Idle after tRC)
READ/READA/
WRIT/WRITA
Illegal
ACTV/
PRE/PALL
Illegal
REF/SELF/
MRS
Illegal
DESL
NOP (Idle after tRSC)
NOP
NOP (Idle after tRSC)
BST Illegal
READ/READA/
WRIT/WRITA
Illegal
ACTV/PRE/
PALL/REF/
SELF/MRS
Illegal
Notes
ABBREVIATIONS:
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
All entries in OPERATION COMMAND TABLE assume the CKE was High during the proceeding clock
cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shut down.
Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
Illegal if any bank is not idle.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to TIMING DIAGRAM -11 & -12.
NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
SELF command should only be issued after the last read data have been appeared on DQ.
MRS command should only be issued on condition that all DQ are in Hi-Z.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB81F641642D.PDF ] | |
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