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PDF TMP90C802A Data sheet ( Hoja de datos )
| Número de pieza | TMP90C802A | |
| Descripción | (TMP90C802A / TMP90C803A) CMOS 8-Bit Microcontrollers | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA
TLCS-90 Series
TMP90C802A/803A
CMOS 8–Bit Microcontrollers
(2) Minimum instruction executing time: 320ns
(at 12.5MHz oscillation frequency)
TMP90C802AP/TMP90C802AM
(3) Internal ROM: 8K byte (The TMP90C803A does not
have a built-in ROM.)
TMP90C803AP/TMP90C803AM
(4) Internal RAM: 256 byte
(5) Memory expansion
1. Outline and Characteristics
External memory: 56K byte
The TMP90C802A is a high-speed advanced 8-bit
(6) General-purpose serial interface (1 channel)
microcontroller applicable to a variety of equipment.
With its 8-bit CPU, ROM, RAM, timer/event counter and gen-
eral-purpose serial interface integrated into a single CMOS chip,
mthe TMP90C802A allows the expansion of external memories (up
to 56K byte). The TMP90C803A is the same as the
oTMP90C802A but without the ROM
.cThe TMP90C802AP/803AP is in a DIP product.
The TMP90C802AM/8803AM is in a SOP (Small Outline
Package).
The characteristics of the TMP90C802A include:
t4U(1) Powerful instructions: 163 basic instructions, including
Multiplication, division, 16-bit arithmetic operations, bit
manipulation instructions
Asynchronous mode, I/O interface mode
(7) 8-bit timers (4 channels): (1 external clock input)
(8) Port with zero cross detection circuit (1 input)
(9) Input/Output ports (TMP90C802A: 32 pins, 90C803A: 6
pins)
(10) Interrupt function: 8 internal interrupts and 3 external
interrupts
(11) Micro Direct Memory Access (DMA) function
(4 channels)
(12) Watchdog timer
(13) Standby function (4 HALT modes)
www.DataShee taSheet4U.comTheinformationcontainedhereissubjecttochangewithoutnotice.
aThe information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
.Dequipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
wof safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
wwTOSHIBA CORPORATION
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1 page  
TMP90C802A/803A
3. Operation
This chapter describes the functions and the basic operations
of the TMP90C802A in every block.
3.1 CPU
TMP90C802A includes a high performance 8-bit CPU. For the
function of the CPU, see the book TLCS Series CPU Core
Architecture concerning CPU operation. This chapter
explains exclusively the functions of the CPU of TMP90C802A
which are not described in that book.
3.1.1 Reset
The basic timing of the reset operation is indicated in Figure
3.1. In order to reset the TMP90C802A, the RESET input must
be maintained at the “0” level for at least ten system clock
cycles (10 stated: 2µsec at 10MHz) within an operating voltage
band and with a stable oscillation. When a reset request is
accepted, all I/O ports (Port 0/data bus D0 ~ D7, Port 1/
address bus A0 to A7, Port 2/address bus A8 to A15) function
as input ports (high impedance state). Output ports (P32, P33,
P35 (RD) and P36 (WR) and CLK turn to “1”. Input ports
remain unchanged.
The registers of the CPU also remain unchanged. Note,
however, that the program counter “PC” and the interrupt
enable flag IFF are cleared to “0”. Register A shows an undefined
status.
When the reset is cleared, the CPU starts executing
instructions from the address 0000H.
Figure 3.1. Reset Timing
3.1.2 EXF (Exchange Flag)
For TMP90C802A, “EXF”, which is inverted when the com-
mand “EXX” is executed to transfer data between the main
register and the auxiliary register, is allocated to the first bit of
memory address FFD2H.
TOSHIBA CORPORATION
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5 Page 
TMP90C802A/803A
Figure 3.3 (3). Micro DMA Processing Flowchart
The micro DMA processing is performed by using only
hardware to process interrupts mostly completed by simple data
transfer. The use of hardware allows the micro DMA processing
to handle the interrupt in a higher speed that the conventional
methods using software. the CPU registers are not affected by
the micro DMA processing.
Figure 3.3 (4) shows the functions of parameters used in
the micro DMA processing.
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