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PDF TMP90C848F Data sheet ( Hoja de datos )

Número de pieza TMP90C848F
Descripción CMOS 8-Bit Microcontrollers
Fabricantes Toshiba 
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TOSHIBA
TLCS-90 Series
TMP90C848F
CMOS 8–Bit Microcontrollers
TMP90C848F
1. Outline and Characteristics
The TMP90C848F is a high-end 8-bit microcontroller developed (4) Built-in RAM: 512 bytes
in order to control power supply switching. With built-in high-speed (5) High-speed flash A/D converter (standard conversion
16-channel flush A/D converter (conversion time: 1.6 microseconds
time: 1.6 microseconds, 16 channels)
@10MHz*), high-speed 8-channel PWM (8-bit resolution,
oscillation frequencies of 80KHz, 160KHz, and 320KHz
@10MHz*) and a clock switching function, the TMP90C848F
mis ideal for controlling compact personal computer power
supplies. (* indicates a CPU clock with a 20MHz external
oclock (X1), which is divided by 2 during high-speed opera-
tion.)
.cThe TMP90C848F is a CMOS 8-bit microcontroller which
integrates an 8-bit CPU, ROM, RAM, an A/D converter, a
multi-function timer, serial interface, high-speed PWM, and a
Uclock switching function in a single chip.
The characteristics of the TMP90C848F are as follows:
t4(Assuming high-speed external clock X1 = 20MHz, CPU clock
fc = 10MHz)
e(1) Highly efficient instructions (TLCS-90 instruction sets)
e163 types of basic instructions, including
Multiplication/division arithmetic, 16-bit arithmetic
hoperation, bit manipulation instruction.
S(2) Minimum instruction executing time: 400ns
(3) Built-in ROM: 8K bytes
(6) General-purpose serial interface (1 channel)
(7) High-speed PWM output (8 channels, effective only at
high-speed clock operation)
Oscillation frequency: 80KHz, 160KHz, 320KHz
Resolution: 8 bits (50ns, 25ns, 12.5ns)
(8) Multi-function 16-bit timer/event counter: 1
(9) 8-bit timer: 4 channel
(10) Input/Output port: 62 pins
(11) Micro DMA function (11 channels)
(12) Watchdog timer function (internally connectable to
hardware reset)
(13) Interrupt function: 10 internal; 3 external
(14) Clock switching function (high-speed/low-speed
switching)
(15) Standby function (3 HALT modes, possible to disable
setting STOP mode.)
(16) Standby function (3 HALT modes, standby mode disable.)
www.Data taSheet4U.comThe information contained here is subject to change without notice.
aThe information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
.Dequipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
wof safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
wwTOSHIBA CORPORATION
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TMP90C848F pdf
Pin name
CLK
EA
RESET
X1/X2
X1/X2
TEST1/TEST2
A VCC
VREF
AVSS
VCC
VSS
TMP90C848F
No. of pins
1
1
1
2
2
2
1
1
1
2
3
I/O or tristate
Output
Input
Input
I/O
I/O
I/O
Table 2.2 (2/2)
Function
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. Pulled up internally during
resetting.
External access: Connected to the VCC pin when using the TMP90C848F with built-in ROM.
Reset: Initializes the TMP90C848F.
High-speed crystal oscillator connection pin.
Low-speed crystal oscillator connection pin.
Testing pins: Connects directly TEST1 and TEST2 at a normal state operation.
Comparator power supply for the A/D converter.
A/D converter reference voltage input.
Analog GND pin (0V)
Power supply pin (+ 5V ± 10%)
GND pin (0V)
TOSHIBA CORPORATION
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TMP90C848F arduino
TMP90C848F
3.3.1 General Purpose Interrupt Processing
Figure 3.3 (2)shows the flow of general-purpose interrupt
processing.
The CPU first saves the contents of the program counter
PC and register AF (including the interrupt enable/disable flag
just before the interrupt is issued) into the stack, and resets the
interrupt enable/disable flag IFF to “0” (interrupt disable).
Finally, it transfers the contents “V” of interrupt vector to the
program counter and jumps to the interrupt processing program.
The overhead for the entire process from accepting an
interrupt to jumping to an interrupt processing program is 20
states.
Figure 3.3 (2). General Purpose Interrupt Processing Flowchart
The interrupt processing program ends with RETI instruction
for both non-maskable and maskable interrupts.
When this instruction is executed, the contents of the program
counter PC and register AF will be restored from the stack
(returns to the interrupt enable/disable flag just before the
interrupt was issued).
When the CPU reads an interrupt vector, the interrupt
request source acknowledges that the CPU accepts the
request, and clears the request.
Non-maskable interrupts cannot be disabled by program.
Maskable interrupts, however, can be enabled or disabled by
programming. An interrupt enable/disable flip-flop (IFF) is provided
on the bit 5 of Register F in the CPU.
Interrupts are enabled by setting IFF to “1” with the EI
instruction and disabled by resetting IFF to ”0” with the DI
instruction. IFF is reset to “0” by the reset operation or the
acceptance of any interrupt (including non-maskable interrupts).
Interrupt enabled with the EI instruction become effective
when the instruction after the EI is executed.
Table 3.3 (1) shows the interrupt sources.
TOSHIBA CORPORATION
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