PDF AS4C256K16E0 Data sheet ( Hoja de datos )

Número de pieza	AS4C256K16E0
Descripción	5V 256K x 16 CMOS DRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! AS4C256K16E0 ® 5V 256K×16 CMOS DRAM (EDO) Features • Organization: 262,144 words × 16 bits • Refresh • High speed - 512 refresh cycles, 8 ms refresh interval - 30/35/50 ns RAS access time - RAS-only or CAS-before-RAS refresh or self-refresh - 16/18/25 ns column address access time - Self-refresh option is available for new generation device - 7/10/10/10 ns CAS access time only. Contact Alliance for more information. • Low power consumption • Read-modify-write - Active: 500 mW max (AS4C256K16E0-25) • TTL-compatible, three-state I/O - Standby: 3.6 mW max, CMOS I/O (AS4C256K16E0-25) • EDO page mode .comPin arrangement SOJ UVcc I/O0 t4I/O1 I/O2 I/O3 Vcc eI/O4 I/O5 eI/O6 I/O7 NC hNC WE RAS SNC A0 taA1 A2 A3 aVcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TSOP II GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 VCC 1 I/O0 2 I/O1 3 I/O2 4 I/O3 5 VCC 6 I/O4 7 I/O5 8 I/O6 9 I/O7 10 NC LCAS UCAS NC 13 OE NC 14 A8 WE 15 A7 RAS 16 A6 NC 17 A5 A0 18 A4 A1 19 GND A2 20 A3 21 VCC 22 44 GND 43 I/O15 42 I/O14 41 I/O13 40 I/O12 39 GND 38 I/O11 37 I/O10 36 I/O9 35 I/O8 32 NC 31 LCAS 30 UCAS 29 OE 28 A8 27 A7 26 A6 25 A5 24 A4 23 GND • JEDEC standard packages - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II • 5V power supply • Latch-up current > 200 mA Pin designation Pin(s) Description A0 to A8 Address inputs RAS Row address strobe I/O0 to I/O15 Input/output OE Output enable UCAS Column address strobe, upper byte LCAS Column address strobe, lower byte WE Read/write control VCC GND Power (5V ± 0.5V) Ground .DSelection guide wMaximum RAS access time wMaximum column address access time mMaximum CAS access time w .coMaximum output enable (OE) access time UMinimum read or write cycle time t4Minimum EDO page mode cycle time eeMaximum operating current hMaximum CMOS standby current SShaded areas contain advance information. Symbol tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC2 AS4C256K16E0-30 30 16 10 10 65 12 180 2.0 AS4C256K16E0-35 35 18 10 10 70 14 160 2.0 AS4C256K16E0-50 50 25 10 10 85 25 140 2.0 Unit ns ns ns ns ns ns mA mA www.Data4/11/01; v.1.1 Alliance Semiconductor 1 of 24 Copyright © Alliance Semiconductor. All rights reserved. 1 page Write cycle Std Symbol Parameter tASC Column address setup time tCAH Column address hold time tAWR Column address hold time to RAS tWCS Write command setup time tWCH Write command hold time tWCR Write command hold time to RAS tWP Write command pulse width tRWL Write command to RAS lead time tCWL Write command to CAS lead time tDS Data-in setup time tDH Data-in hold time tDHR Data-in hold time to RAS Shaded areas contain advance information. Read-modify-write cycle Std Symbol Parameter tRWC Read-write cycle time tRWD RAS to WE delay time tCWD CAS to WE delay time tAWD Column address to WE delay time tRSH(W) CAS to RAS hold time (write) tCAS(W) CAS pulse width (write) Shaded areas contain advance information. AS4C256K16E0 ® -30 Min Max 0– 5– 26 – 0– 5– 26 – 5– 10 – 10 – 0– 5– 26 – -35 Min Max 0– 5– 28 – 0– 5– 28 – 5– 11 – 11 – 0– 5– 28 – -50 Min Max Unit 0 – ns 9 – ns 30 – ns 0 – ns 9 – ns 30 – ns 9 – ns 12 – ns 12 – ns 0 – ns 9 – ns 30 – ns Notes 11 11 12 12 -30 Min Max 100 – 50 – 26 – 32 – 10 – 15 – -35 Min Max 105 – 54 – 28 – 35 – 10 – 15 – -50 Min Max 120 – 60 – 30 – 40 – 12 – 15 – Unit ns ns ns ns ns ns Notes 11 11 11 4/11/01; v.1.1 Alliance Semiconductor 5 of 24 5 Page AS4C256K16E0 ® Upper byte write cycle waveform RAS Address UCAS LCAS WE OE Upper I/O Lower I/O tRAS tRC tRP tRAD tASR tRAH Row Address tCRP tAWR tRAL Column Address tRCD tCSH tASC tRSH tCAH tCAS tCRP tCRP tCWL tWP tRPC tRWL tOEH tDS Data In tOED tDH (OE controlled) Lower byte write cycle waveform RAS Address tASR tRAD tRAH Row Address LCAS UCAS tCRP tCRP WE OE Upper I/O Lower I/O tRAS tRC tAWR tRAL Column Address tRCD tCSH tACS tCAH tCAS tRSH tCWL tRWL tWP tOEH tDS Data In tDH (OE controlled) tRP tCRP tRPC 4/11/01; v.1.1 Alliance Semiconductor 11 of 24 11 Page

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