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PDF LM6225N Data sheet ( Hoja de datos )
| Número de pieza | LM6225N | |
| Descripción | High Speed Buffer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 1994
LM6125/LM6225/LM6325
High Speed Buffer
General Description
The LM6125 family of high speed unity gain buffers slew at
800 V/µs and have a small signal bandwidth of 50 MHz while
driving a 50Ω load. These buffers drive ±300 mA peak and
do not oscillate while driving large capacitive loads. The
LM6125 contains unique features not found in power buffers;
these include current limit, thermal shutdown, electronic
shutdown, and an error flag that warns of fault conditions.
These buffers are built with National’s VIP™ (Vertically Inte-
grated PNP) process which provides fast PNP transistors
that are true complements to the already fast NPN devices.
This advanced junction-isolated process delivers high speed
performance without the need for complex and expensive di-
electric isolation.
n High output current: ±300 mA
n Stable with large capacitive loads
n Current and thermal limiting
n Electronic shutdown
n 5V to ±15V operation guaranteed
n Fully specified to drive 50Ω lines
Applications
n Line Driving
n Radar
n Sonar
Features
n High slew rate: 800 V/µs
Simplified Schematic and Block Diagram
DS009222-1
Numbers in () are for 14–pin N DIP.
VIP™ is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS009222
DS009222-2
www.national.com
1 page  
AC Electrical Characteristics (Continued)
Note 5: For operation at elevated temperature, these devices must be derated based on a thermal resistance of θJA and TJ max, TJ = TA + θJA PD. θJC for the
LM6125H and LM6225H is 17˚C/W. The thermal impedance θJA of the device in the N package is 40˚C/W when soldered directly to a printed circuit board, and the
heat-sinking pins (pins 3, 4, 5, 10, 11, and 12) are connected to 2 square inches of 2 oz. copper. When installed in a socket, the thermal impedance θJA of the N pack-
age is 60˚C/W.
Note 6: Limits are guaranteed by testing or correlation.
Note 7: The input is biased to +2.5V, and VIN swings VPP about this value. The input swing is 2 VPP at all temperatures except for the AV3 test at −55˚C where it
is reduced to 1.5 VPP.
Note 8: The Error Flag is set (low) during current limit or thermal fault detection in addition to being set by the Shutdown pin. It is an open-collector output which re-
quires an external pullup resistor.
Note 9: Slew rate is measured with a ±11V input pulse and 50Ω source impedance at 25˚C. Since voltage gain is typically 0.9 driving a 50Ω load, the output swing
will be approximately ±10V. Slew rate is calculated for transitions between ±5V levels on both rising and falling edges. A high speed measurement is done to minimize
device heating. For slew rate versus junction temperature see typical performance curves. The input pulse amplitude should be reduced to ±10V for measurements
at temperature extremes. For accurate measurements, the input slew rate should be at least 1700 V/µs.
Note 10: The test circuit consists of the human body model of 120 pF in series with 1500Ω.
Note 11: A military RETS specification is available on request. At the time of printing, the LM6125H/883 RETS spec complied with the Boldface limits in this column.
The LM6125H/883 may also be procured as Standard Military Drawing specification #5962-9081501MXX.
Typical Performance Characteristics TA = 25˚C, VS= ± 15V unless otherwise specified
Frequency Response
Frequency Response
Slew Rate vs Temperature
DS009222-9
Overshoot vs Capacitive Load
DS009222-10
Large Signal Response
(RL = 1 kΩ)
DS009222-11
Large Signal Response
(RL = 50Ω)
Supply Current
DS009222-12
−3 dB Bandwidth
DS009222-13
Slew Rate
DS009222-14
DS009222-15
DS009222-16
5
DS009222-17
www.national.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet LM6225N.PDF ] | |
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