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PDF CXD2755Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2755Q | |
| Descripción | Super Audio CD Format Book Annex D&E Conformalmetering | |
| Fabricantes | Sony Electronics | |
| Logotipo |  |
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CXD2755Q
Super Audio CD Format Book ANNEX D&E Conformal Metering
Description
The CXD2755Q is the signal processor for signal
level measurement of DSD (Direct Stream Digital)
conformed to ANNEX D&E of Super Audio CD Format
Book V1.2. This LSI can measure up to 8 channel
DSD signals to detect the maximum level of each
frequency band specified in ANNEX D&E of Super
Audio CD format and output the peak values of every
44.1kHz cycle for the signal level measurement and
display.
Functions
• Up to 8 channels of 1bit, 2.8224MHz (44.1kHz × 64)
DSD input supported.
• MaxPeak measurement (ANNEX D3):
28-tap 1st-order moving average filter is used for
MaxPeak level measurement.
• DC removal filter:
DC removal filter (fc = about 0.1Hz) is inserted to
HF/MF/LF filters.
• HF measurement (ANNEX D4):
40kHz 5th-order Butterworth high-pass filter and
100kHz 5th-order Butterworth low-pass filter are
used for HF band measurement. In addition,
"Mean-Square" and "Square-Root" are calculated
for RMS metering.
• MF measurement (ANNEX E2):
20kHz 10th-order Butterworth high-pass filter and
50kHz 5th-order Butterworth low-pass filter are
used for MF band measurement.
• LF measurement:
20kHz 10th-order Butterworth low-pass filter is
used for LF band measurement.
• DC measurement (ANNEX E4):
0.1Hz 2nd-order low-pass filter is used for DC
measurement.
• MF over warning flag (ANNEX E2):
As the MF specification has the exceptional
condition for warning, the signal level of MF and
LF are continuously compared and output the
warning status from this LSI.
208 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD VSS – 0.5 to + 4.6 V
• Input voltage
VI VSS – 0.5 to VDD + 0.5 V
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage VDD
3.0 to 3.6
• Operating temperature
Topr –10 to +75
V
°C
Input/Output Capacitance
• Input capacitance CI
• Output capacitance CO
Max. 9pF
Max. 11pF
Note) Measurement conditions
VDD = VI = 0V, fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02559-PS
1 page  
Pin
No.
Symbol
I/O
Description
36 VSS
37 MONSEL0 Ipd NC.
38 MONSEL1 Ipd NC.
39 MONSEL2 Ipd NC.
40 MONSEL3 Ipd NC.
41 VSS
42 NC
43 NC
44 NC
45 VDD
46 VSS
47 TCK
Ipu NC.
48 TDI
Ipu NC.
49 TENA1
Ipu NC.
50 TRST
Ipu Fixed to Low level or input Power on reset signal.
51 TDO
O NC.
52 VST
GND. (VSS for test circuit)
53 VSS
54 NC
55 NC
56 NC
57 VDD
58 VSS
59 NC
60 CSEL0
I
Channel select input 0 for 8-channel output stream.
(Normally, 4Fs clock should be input.)
61 CSEL1
I
Channel select input 1 for 8-channel output stream.
(Normally, 2Fs clock should be input.)
62 CSEL2
I
Channel select input 2 for 8-channel output stream.
(Normally, 1Fs clock should be input.)
63 VSS
64 NC
65 NC
66 8BCKI
Isc
Bit clock input for 8-channel output stream.
(Normally, 256Fs clock should be input.)
67 VDD
68 VSS
69 NC
∗ Isc: Hysteresis (Schmitt) input / Ipu: Pulled-up input / Ipd: Pulled-down input
–5–
CXD2755Q
5 Page 
CXD2755Q
2. Output for 2-Channel Meter (FSCKI, FSCKO, 2BCKI, 2∗∗∗O) (VDD = 3.0 to 3.6V, Topr = –20 to +75°C)
Item
FSCKI frequency
FSCKO rise time from FSCKI rise
2BCKI frequency
2BCKI clock pulse width (High)
2BCKI clock pulse width (Low)
FSCKO setup time, relative to 2BCKI rise
FSCKO hold time, relative to 2BCKI rise
2BCKI fall setup time, relative to MCKI rise
2BCKI rise setup time, relative to MCKI rise
2∗∗∗O change time from 2BCKI fall
Symbol
ffscki
tfsckodly
f2bcki
tw2bckih
tw2bckil
tsufscko
thdfscko
tsu2bckil
tsu2bckih
t2∗∗∗odly
Min.
—
–39.2∗1
—
143
143
143
143
2.3
2.2
12.1
Typ.
44.1
10.7∗2
2.8224
177
177
177
177
5.0
4.7
25.6
Max.
—
66.5∗3
—
211
211
211
211
10.3
9.8
52.9
Unit
kHz
ns
MHz
ns
ns
ns
ns
ns
ns
ns
∗1 Minimum gate delay –1MCK
∗2 Typical gate delay
∗3 Maximum gate delay +1MCK
FSCKI
1/ffscki
FSCKO
tfsckodly
MCKI
FSCKO
2BCKI
2∗∗∗O
1/f2bcki
tw2bckih
tw2bckil
thdfscko
tsu2bckil
tsufscko
tsu2bckih
t2∗∗∗odly
– 11 –
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CXD2755Q.PDF ] | |
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