|
|
PDF MS81V26000 Data sheet ( Hoja de datos )
| Número de pieza | MS81V26000 | |
| Descripción | Field Memory | |
| Fabricantes | OKI Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MS81V26000 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
OMKSI8S1ShVeem2et6i4c0Uo0.cn0odmuctor1,114,112-Word × 24-Bit Field Memory
FEDSMS81V26000-02
Issue Date: Dec 15, 2004
w.DataGENERAL DESCRIPTION
ww The OKI MS81V26000 is a high performance 26-Mbit, 1,100K × 24-bit, Field Memory. It is especially designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and
Multi-media systems. MS81V26000 is a FRAM for wide or low end use in general commodity TVs and VTRs
exclusively. MS81V26000 is not designed for the other use or high end use in medical systems, professional
mgraphics systems which require long term picture storage, data storage systems and others. More than two
MS81V26000s can be cascaded directly without any delay devices among the MS81V26000s. (Cascading of
oMS81V26000 provides larger storage depth or a longer delay).
.cEach of the 24-bit planes has separate serial write and read ports. These employ independent control clocks to
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data
Urates between write and read data streams.
t4The MS81V26000 provides high speed FIFO, First-In First-Out, operation without external refreshing:
MS81V26000 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
eoperation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
epower is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.
hThe MS81V26000’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by
Sreset timing. The delay length, number of read delay clocks between write and read, is determined by externally
controlled write and read reset timings.
taAdditionally, the MS81V26000 has write mask function or input enable function (IE), and read-data skipping
afunction or output enable function (OE) . The differences between write enable (WE) and input enable (IE), and
between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address
increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to
.DMS81V26000. The input enable (IE) function allows the user to write into selected locations of the memory only,
leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture”
wwwon a TV screen.
www.DataSheet4U.com
1/20
1 page  
OKI Semiconductor
FEDS81V26000-02
MS81V26000
PIN DESCRIPTION
Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.
Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MS81V26000 is in fully static operation as long as the power is on. Note that WE setup
and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 4.
After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at
address 0 is started after a time tWL form the cycle in which WE is brought high.
After write reset, WE should be remained high for 2 cycles after driving WE high first.
Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK. The latency for the write operation control by IE is 4.
Write Address Input: WAD
These pins are used for write address input.
Data Inputs: (DI0-23)
These pins are used for serial data inputs.
Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.
Data Out: (DO0-23)
These pins are used for serial data outputs.
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS81V26000.
Read Reset: RSTR
RSTR is used to set the internal read address pointer. RSTR setup and hold times are referenced to the rising edge
of SRCK. The SWCK latches the read address data (21bits serial LSB) from RAD.
Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the
SRCK clock.
5/20
5 Page 
OKI Semiconductor
FEDS81V26000-02
MS81V26000
New Data Read Access
In order to read out “new data,” i.e., to read out data that has been written in a follow-up manner, read reset must be
input after write address 150 and the difference between the read address and the write address must be 350 or
more but 1,114,111 or less.
Old Data Read Access
In order to read out “old data,” i.e., to read out data that was written prior to the write operation being carried out,
the difference between the read address and the write address must be 0 or more but 30 or less. If the difference
between the read address and the write address is between 31 and 349 or 1,114,112 or more, it is unpredictable
whether the new data is output or whether the old data is output. In this case, however, the write data will be written
normally.
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MS81V26000.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MS81V26000 | Field Memory | OKI Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |