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PDF PLL600-30 Data sheet ( Hoja de datos )

Número de pieza PLL600-30
Descripción (PLL600-10/20/30) Ultra Low Current XO
Fabricantes PhaseLink 
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om PLL600-10/-20/-30Preliminary
.cUltra Low Current XO (Crystals from 10 MHz to 52 MHz)
et4UFEATURES
heLow phase noise (-130 dBc @ 10kHz offset at
taS30MHz).
aCMOS output with OE tri-state control.
.DSelectable oscillator “on” or “off” feature in out-
put disable mode
wUltra Low current consumption (<2.5mA, <2mA,
w<1.3mA at 27MHz respectively for PLL600-10,
w PLL600-20, and PLL600-30)
mUltra Low disable mode current (<2uA when
disabled with osc. off)
o10 to 52MHz fundamental crystal input.
.cSelectable divider by 2 (PLL600-10 only).
12mA drive capability at TTL output.
ULow jitter (RMS): 2.5ps period jitter.
2.25V to 3.63V DC operation.
t4Available in die (fits 5x3.2 low profile substrate).
eDESCRIPTION
eThe PLL600-10/-20/-30 form a low cost family of XO
hdies, designed to consume the lowest current on the
market for the 5MHz to 52MHz range. It accepts in-
Sput crystal from 10 to 52MHz (fundamental resonant
tamode) and offers (PLL600-10 only) a selectable di-
vider by 2 or no division. Providing less than -
130dBc at 10kHz offset at 30MHz, and with a very
alow jitter (2.5 ps RMS period jitter) makes this chip
ideal for applications requiring low current frequency
.Dsources, such as handheld devices.
PAD LAYOUT
8
1
27
6
3
5
4
SELECTION TABLE
SEL (PLL600-10)
DIVIDER
0 /2
1 No division
Internal Pull-up, default value is ‘1’ when not connected.
Selectable divider available on P600-10 only.
OE
OSCSEL
OUTPUT
0
0
Disabled
Osc. Off
0
1
Disabled
Osc. On
1 0 Enabled
1 1 Enabled
Internal Pull-up, default value is ‘1’ when not connected.
wBLOCK DIAGRAM
ww U.comSEL
Reference
Divider
et4XIN
heXOUT
XTAL
OSC
CLK
OE
OSCSEL
www.DataS47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/23/03 Page 1

1 page




PLL600-30 pdf
Preliminary PLL600-10/-20/-30
Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
Name
XOUT
SEL
GND
OSCSEL
CLK
VDD
SEL
XIN
X (µm)
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
Y (µm)
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Die dimensions and reference coordinates in µm excluding scribe lines:
Lower left:
X=0, Y=0
Upper right:
X=812, Y=986
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PART NUMBER
PLL600-XX D C
TEMPERATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
D=Die
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/23/03 Page 5

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