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PDF PLL602-39 Data sheet ( Hoja de datos )
| Número de pieza | PLL602-39 | |
| Descripción | (PLL602-35/37/38/39) Low Phase Noise Multiplier XO | |
| Fabricantes | PhaseLink | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL602-39 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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om PLL602-35/-37/-38/-39Preliminary
.c 750kHz – 800MHz Low Phase Noise Multiplier XO
U Universal Low Phase Noise IC’s
eet4FEATURES
Sh• Selectable 750kHz to 800MHz range.
ta• Low phase noise output (@ 10kHz frequency
aoffset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
.D106.25MHz, -125dBc/Hz for 155.52MHz, -
w110dBc/Hz for 622.08MHz).
w• CMOS (PLL602-37), PECL (PLL602-35 and
w PLL602-38) or LVDS (PLL602-39) output.
• 12 to 25MHz crystal input.
m• No external load capacitor or varicap required.
o• Output Enable selector.
.c• Selectable 1/16 to 32x frequency multiplier.
• 3.3V operation.
• Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
2
3
4
5
6
7
8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
t4UDESCRIPTIONS
The PLL602-35 (PECL with inverted OE), PLL602-37
e(CMOS), PLL602-38 (PECL), and PLL602-39 (LVDS)
eare high performance and low phase noise XO IC
chips. They provide phase noise performance as low
has –125dBc at 1kHz offset (at 155MHz), by multiply-
ing the input crystal frequency up to 32x. They ac-
Scept fundamental parallel resonant mode crystals
tafrom 12 to 25MHz.
XOUT
SEL3^
SEL2^
OE
12 11 10
13
9
8
14 PLL602-3x 7
15 6
16 5
123 4
GND
CLKC
VDD
CLKT
aBLOCK DIAGRAM
.DSEL
wwOscillator
w mX+ Amplifier
t4U.coX-
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
Q
Q
PLL602-3x
^: Internal pull-up
*: On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0
(pin 10), and pin 11 is VDD. See pin assignment table for details.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PLL602-38
0 (Default) Output enabled
1 Tri-state
PLL602-35
PLL602-37
PLL602-39
0 Tri-state
1 (Default) Output enabled
OE input: Logical states defined by PECL levels for PLL602-38
Logical states defined by CMOS levels for PLL602-35/-37/-39
www.DataShee47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 1
1 page  
Preliminary PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
5. Jitter specifications
PARAMETERS
CONDITIONS
Period jitter RMS
With capacitive decoupling between
VDD and GND.
Accumulated jitter RMS
Integrated jitter RMS
With capacitive decoupling between
VDD and GND. Over 10,000 cycles.
Integrated 12 kHz to 20 MHz
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
622.08MHz
155.52MHz
155.52MHz
MIN.
TYP.
5
8
9
10
TBM
3
MAX.
4
UNITS
ps
ps
ps
6. Phase noise specifications
PARAMETERS
Phase Noise relative to
carrier
FREQUENCY
19.44MHz
106.25MHz
155.52MHz
622.08MHz
@10Hz
-60
-60
-60
-60
@100Hz
-90
-90
-90
-90
@1kHz
-112
-112
-112
-109
@10kHz
-140
-127
-125
-110
@100kHz
-150
-125
-123
-109
UNITS
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PLL602-39.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PLL602-35 | (PLL602-35/37/38/39) Low Phase Noise Multiplier XO | PhaseLink |
| PLL602-37 | (PLL602-35/37/38/39) Low Phase Noise Multiplier XO | PhaseLink |
| PLL602-38 | (PLL602-35/37/38/39) Low Phase Noise Multiplier XO | PhaseLink |
| PLL602-39 | (PLL602-35/37/38/39) Low Phase Noise Multiplier XO | PhaseLink |
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