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PDF ICS9112-17 Data sheet ( Hoja de datos )
| Número de pieza | ICS9112-17 | |
| Descripción | Low Skew Output Buffer | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS9112-17 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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m ICS9112-17Integrated
oCircuit
.cSystems, Inc.
Low SktaeSwheOeut4tpUut BufferGeneral Description
.DaThe ICS9112-17 is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL)
wtechnology to align, in both phase and frequency, the REF
winput with the CLKOUT signal. It is designed to distribute
high speed clocks in PC systems operating at speeds
wfrom 25 to 133 MHz.
mICS9112-17 is a zero delay buffer that provides
osynchronization between the input and output. The
synchronization is established via CLKOUT feed back to
.cthe input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
UThe ICS9112-17 has two banks of four outputs controlled
by two address lines. Depending on the selected address
t4line, bank B or both banks can be put in a tri-state mode.
In this mode, the PLL is still running and only the output
buffers are put in a high impedance mode. The test mode
eshuts off the PLL and connects the input directly to the
output buffers (see table below for functionality).
Features
• Zero input - output delay
• Frequency range 25 - 133 MHz (3.3V)
• High loop filter bandwidth ideal for Spread Spectrum
applications.
• Less than 200 ps cycle to cycle Jitter
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 16 pin, 150 mil SSOP & SOIC package
Pin Configuration
eThe ICS9112-17 comes in a sixteen pin 150 mil SOIC or
h16 pin SSOP package. In the absence of REF input, will
be in the power down mode. In this mode, the PLL is turned
Soff and the output buffers are pulled low. Power down mode
provides the lowest power consumption for a standby
tacondition.
aBlock Diagram
16 pin SSOP & SOIC
www.D www.DataSheet4U.com0051J—02/05/04
Functionality
FS2
FS1
CLKA
(1, 4)
CLKB
(1, 4)
CLKOUT
0 0 Tristate Tristate Driven
0 1 Driven Tristate Driven
PLL PLL
PLL
1 0 Bypass Bypass Bypass
Mode Mode Mode
1 1 Driven Driven Driven
Output
Source
PLL
PLL
REF
PLL
PLL
Shutdown
N
N
Y
N
1 page  
ICS9112-17
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded Less.
0051J—02/05/04
Timing diagrams with different loading configurations
5
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| PDF Descargar | [ Datasheet ICS9112-17.PDF ] | |
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