PDF CY7C09569V Data sheet ( Hoja de datos )

Número de pieza	CY7C09569V
Descripción	(CY7C09569V / CY7C09579V) Synchronous Dual Port Static RAM
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY7C09569V (archivo pdf) en la parte inferior de esta página. Total 28 Páginas
No Preview Available ! 1 7C09579V: 10/97 Revision: May 1, 2000 .com CCYY77CC0099556799VVPRELIMINARY Sheet4UFLEx36™ Synchronous Du3a.l3-PVo1rt6SKt/a3t2icKRxA3M6Features ta• True dual-ported memory cells which allow simulta- aneous access of the same memory location .D• Two Flow-Through/Pipelined devices w— 16K x 36 organization (CY7C09569V) w— 32K x 36 organization (CY7C09579V) w • 0.25-micron CMOS for optimum speed/power • Three modes m— Flow-Through o— Pipelined .c— Burst • Bus-Matching Capabilities on Right Port (x36 to x18 or x9) U• Byte-Select Capabilities on Left Port • 133-MHz Pipelined Operation t4• High-speed clock to data access 4.1/5/6/8 ns Logic Block Diagram • 3.3V Low operating power — Active = 260 mA (typical) — Standby = 10 µA (typical) • Fully synchronous interface for ease of use • Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes • Counter Address Read Back via I/O lines • Single Chip Enable • Automatic power-down • Commercial and Industrial Temperature Ranges • Compact package — 144-Pin TQFP (20 x 20 x 1.4 mm) — 172-Ball BGA (1.0 mm pitch) (15 x 15 x .51 mm) eeR/WL hOEL B0–B3 SCEL taFT/PipeL Left Port Control Logic aI/O0L–I/O8L .DI/O9L–I/O17L wI/O18L–I/O26L wI/O27L–I/O35L mA0–A13/14L[1] w oCLKL .cADSL UCNTENL t4CNTRSTL 14/15 9 9 9 9 Counter/ Address Register Decode heeNote: 1. A0–A13 for 16K; A0–A14 for 32K devices. I/O Control I/O Control True Dual-Ported RAM Array Right Port Control Logic 9 9 Bus 9 Match 9 Counter/ Address Register Decode R/WR OER CER FT/PipeR BE 9/18/36 I/OR 14/15 BM SIZE A0–A13/14R[1] CLKR ADSR CNTENR CNTRSTR w.DataSFor the most recent information, visit the Cypress web site at www.cypress.com wwCypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 1, 2000 1 page 7C09579V: 10/97 Revision: May 1, 2000 PRELIMINARY CY7C09569V CY7C09579V Selection Guide CY7C09569V CY7C09569V CY7C09569V CY7C09569V CY7C09579V CY7C09579V CY7C09579V CY7C09579V -133 -100 -83 -67 fMAX2 (MHz) (Pipelined) Max. Access Time (ns) (Clock to Data, Pipelined) 133 100 4.1 5 83 6 67 8 Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (µA) (Both Ports CMOS Level) 260 35 10 µA 250 30 10 µA 240 25 10 µA 230 25 10 µA Pin Definitions Left Port A0L–A13/14L ADSL CEL CLKL CNTENL CNTRSTL I/O0L–I/O35L OEL R/WL FT/PIPEL B0L–B3L Right Port A0R–A13/14R ADSR CER CLKR CNTENR CNTRSTR I/O0R–I/O35R OER R/WR FT/PIPER Description Address Inputs (A0–A13 for 16K, A0–A14 for 32K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to assert the part using the externally supplied address on Address Pins. To load this address into the Burst Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST is asserted LOW Chip Enable Input. Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec- tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output. Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Byte Select Inputs. Asserting these signals enable read and write operations to the correspond- ing bytes of the memory array. BM, SIZE Select Pins for Bus Matching. See Bus Matching for details. BE Big Endian Pin. See Bus Matching for details. VSS Ground Input. VDD Power Input. 5 5 Page 7C09579V: 10/97 Revision: May 1, 2000 PRELIMINARY Switching Waveforms (continued) Bus Match Read Cycle for Pipelined Operation (FT/PIPE = VIH)[9, 11, 13, 14, 15] tCYC2 tCH2 tCL2 CLK CY7C09569V CY7C09579V CE R/W ADS tSC tHC tSW tHW ADDRESS An An An+1 An+1 DATAOUT tSA tHA tCD2 tCLKZ tCD2 Qn tCD2 Qn 1 Latency OE LOW Bank Select Pipelined Read[16, 17] tDC 1st Cycle tDC 2nd Cycle CLKL ADDRESS(B1) CE(B1) tSA tSC tCYC2 tCH2 tCL2 tHA A0 tHC A1 tCD2 A2 A3 tSC tHC tCD2 tCKHZ A4 tCD2 DATAOUT(B1) ADDRESS(B2) tSA A0 tHA CE(B2) DATAOUT(B2) tSC tHC A1 Q0 tDC A2 tSC tHC Q1 tDC A3 tCD2 tCKLZ tCKLZ A4 tCKHZ Q2 Qn+1 tDC 1st Cycle A5 tCKHZ Q3 A5 tCD2 tCKLZ Q4 Notes: 16. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 17. B0 = B1 = B2 = B3 = BM = SIZE = ADS = CNTEN = VIL, CNTRST = VIH. 11 11 Page

Páginas	Total 28 Páginas
PDF Descargar	[ Datasheet CY7C09569V.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C09569V	(CY7C09569V / CY7C09579V) Synchronous Dual Port Static RAM	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar