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PDF MT46V2M32V1 Data sheet ( Hoja de datos )
| Número de pieza | MT46V2M32V1 | |
| Descripción | DOUBLE DATA RATE DDR SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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PRELIMINARY
D(DODURB)taLSSEhDeDeRt4AAUT.McAomRATE MMTT4466VV22MM3322V-15-1521K2xK3Dx2D63x24R4MxSb4Dba:RbnxaAkn3sMk2sFor the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
.DaFEATURES
w• Bidirectional data strobe (DQS) transmitted/
wreceived with data, i.e., source-synchronous data
w capture
m• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
o• Reduced output drive option
• Differential clock inputs (CK and CK#)
.c• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
U• DLL to align DQ and DQS transitions with CK
t4• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
e• 32ms, 4,096-cycle auto refresh (7.8µs/cycle)
• Auto precharge option
e• Auto Refresh and Self Refresh Modes
h• Programmable I/O (SSTL_2 compatible) – reduced
and impedance matched
SOPTIONS
ta• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
a• Power Supply
2.5V VDD/VDDQ
.D2.65V VDD/VDDQ
• Plastic Package
100-pin TQFP (0.65mm lead pitch)
w• Timing - Cycle Time
200 MHz @ CL = 3
183 MHz @ CL = 3
w166 MHz @ CL = 3
m150 MHz @ CL = 3
MARKING
2M32
V1
none
LG
-5
-55
-6
-65
w .coPart Number Example:
MT46V2M32V1LG-5
eet4U64Mb (x32) DDR SDRAM PART NUMBER
ShPART NUMBER
.DataMT46V2M32LG
ARCHITECTURE
2 Meg x 32
PIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
(Normal Bend Shown)
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
VREF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
KEY TIMING PARAMETERS
SPEED
GRADE
-5
-55
-6
-65
CLOCK RATE
CL = 2**
CL = 3**
125 MHz
100 MHz
100 MHz
100 MHz
200 MHz
183 MHz
166 MHz
150 MHz
DATA-OUT ACCESS
WINDOW* WINDOW
1.5ns
1.8ns
1.9ns
2.1ns
±0.75ns
±0.75ns
±0.75ns
±0.75ns
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.5ns
+0.5ns
*Minimum clock rate @ CL = 3
**CL = CAS (Read) Latency
ww64Mb: x32 DDR SDRAM
w2M32DDR-07.p65 – Rev. 12/01
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
1 page  
PRELIMINARY
64Mb: x32
DDR SDRAM
PIN DESCRIPTIONS
TQFP PIN NUMBERS
55, 54
SYMBOL TYPE
CK, CK# Input
53 CKE Input
28 CS# Input
27, 26, 25
23, 56, 24, 57
RAS#, CAS#, Input
WE#
DM0-DM3 Input
29, 30
31-34, 47-51, 45, 36
BA0, BA1 Input
A0-A10 Input
97, 98, 100, 1, 3, 4, 6, 7
60, 61, 63, 64, 68, 69, 71, 72
9, 10, 12, 13, 17, 18, 20, 21
74, 75, 77, 78, 80, 81, 83, 84
DQ0-31
I/O
DESCRIPTION
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE
in any bank). CKE is synchronous for POWER-DOWN entry and
exit, and for SELF REFRESH entry. CKE is asynchronous for SELF
REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VDD is applied.
Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A8) for READ/
WRITE commands, to select one location out of the memory array
in the respective bank. A8 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A8 LOW, bank selected by BA0, BA1) or all banks (A8
HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Input/Output:
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
(continued on next page)
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
5 Page 
Commands
Truth Table 1 provides a quick reference of avail-
able commands. This is followed by a verbal descrip-
tion of each command. Two additional Truth Tables
PRELIMINARY
64Mb: x32
DDR SDRAM
appear following the Operation section; these tables
provide current state/next state information.
TRUTH TABLE 1 – COMMANDS
(Note: 1)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
CS# RAS# CAS# WE# ADDR NOTES
HXXX X 9
L HHH
X
9
L L H H Bank/Row 3
L H L H Bank/Col 4
L H L L Bank/Col 4
L HH L
X
8
L LHL
Code
5
L L L H X 6, 7
L L L L Op-Code 2
TRUTH TABLE 1A – DM OPERATION
NAME (FUNCTION)
Write Enable
Write Inhibit
DM DQs NOTES
L Valid 10
HX
10
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-
code to be written to the selected mode register.
3. BA0-BA1 provide bank address and A0-A10 provide row address.
4. BA0-BA1 provide bank address; A0-A7 provide column address; A8 HIGH enables the auto precharge feature (nonpersis-
tent), and A8 LOW disables the auto precharge feature.
5. A8 LOW: BA0-BA1 determine which bank is precharged.
A8 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE during self
refresh.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet MT46V2M32V1.PDF ] | |
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