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PDF MT46V16M8 Data sheet ( Hoja de datos )
| Número de pieza | MT46V16M8 | |
| Descripción | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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m 128Mb: x4, x8, x16 DDR SDRAM
o Features
Double eDeat4tUa.c Rate (DDR) SDRAMMT46V32M4 – 8 Meg x 4 x 4 Banks
ShMT46V16M8 – 4 Meg x 8 x 4 Banks
ataMT46V8M16 – 2 Meg x 16 x 4 Banks
.DFor the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/sdram
wwFeatures
w• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
m• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR 400)
• Bidirectional data strobe (DQS) transmitted/
oreceived with data, i.e., source-synchronous data
.ccapture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
U• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
t4• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
e• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
e• Data mask (DM) for masking write data (x16 has two
– one per byte)
h• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
S• Longer lead TSOP for improved reliability (OCPL)
ta• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)
aTable 1: Configuration Addressing
.DConfiguration
wRefresh Count
Row Addressing
wBank Addressing
Column Addressing
32 Meg x 4
8 Meg x 4 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
2K (A0–A9, A11)
Options
Marking
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
• Plastic Package – OCPL
66-pin TSOP
66-pin TSOP (lead-free)
• Timing – Cycle Time
32M4
16M8
8M16
TG
P
5ns @ CL = 3 (DDR400)
-5B
6ns @ CL = 2.5 (DDR333) (TSOP only)
-6T
7.5ns @ CL = 2 (DDR266)
7.5ns @ CL = 2 (DDR266A)
7.5ns @ CL = 2.5 (DDR266B)
• Self Refresh
Standard
Low Power Self Refresh
• Temperature Rating
Commercial (0°C to 70°C)
Industrial (-40°C to +85°C)
-75E
-75Z
-75
None
L
None
IT
• Revision
:D
16 Meg x 8
4 Meg x 8 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
8 Meg x 16
2 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
w U.comTable 2:
Key Timing Parameters
CL = CAS (READ) latency; minimum clock rate @ CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and CL = 3 (-5B)
eet4Speed Grade
h-5B
S-6T
ta-75E/-75Z
a-75
CL = 2
133 MHz
133 MHz
133 MHz
100 MHz
Clock Rate
CL = 2.5
167 MHz
167 MHz
133 MHz
133 MHz
CL = 3
200 MHz
N/A
N/A
N/A
Data Out
Window
1.6ns
2.0ns
2.5ns
2.5ns
Access
Window
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ
Skew
+0.40ns
+0.45ns
+0.50ns
+0.50ns
w.DPDF: 09005aef816fd013/Source: 09005aef816ce127
w128MBDDRx4x8x16D_1.fm - Rev. C 4/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
wProducts and specifications discussed herein are subject to change by Micron without notice.
1 page  
128Mb: x4, x8, x16 DDR SDRAM
List of Figures
List of Figures
Figure 1:
Figure 1:
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Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Figure 52:
128Mb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
32 Meg x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
16 Meg x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
8 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
66-Pin TSOP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤3 . . . . . . . . . . . . . . . . . . . . . .18
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE to READ - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE to READ - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
WRITE to READ - Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
WRITE to PRECHARGE - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITE to Precharge – Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
WRITE to PRECHARGE Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Data Output Timing – tAC and tDQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Initialize and Load Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Bank Read – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Bank Read – With Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Bank Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Bank Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Write – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
66-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
PDF: 09005aef816fd013/Source: 09005aef816ce127
128MBDDRx4x8x16DLOF.fm - Rev. C 4/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
5 Page 
128Mb: x4, x8, x16 DDR SDRAM
Pin Descriptions Tables
Table 1: Pin Descriptions (Continued)
TSOP
Numbers
2, 4, 5,
7, 8, 10
11, 13, 54, 56,
57, 59, 60, 62,
63,
65
14, 17, 25, 42,
43, 53
2, 5, 8,
11, 56, 59, 62,
65
14, 17, 20, 25,
42, 43, 53
4, 7, 10, 13, 16,
54, 57, 60, 63
5, 11, 56,
62
14, 16, 17, 20,
25, 42, 43, 53
2, 4, 7, 8, 10,
13, 16, 54, 57,
59, 60, 63, 65
51
16
51
Symbol
DQ0–DQ2
DQ3–DQ5
DQ6–DQ8
DQ9–DQ11
DQ12–DQ14
DQ15
NC
DQ0–DQ2
DQ3–DQ5
DQ6, DQ7
NC
NF
DQ0–DQ2
DQ3
NC
NF
DQS
LDQS
UDQS
19, 50
3, 9, 15, 55, 61
DNU
VDDQ
6, 12, 52, 58,
64
1, 18, 33
34, 48, 66
49
VSSQ
VDD
VSS
VREF
Type
I/O
Description
Data Input/Output: Data bus for x16
– No Connect for x16
These pins should be left unconnected.
I/O Data Input/Output: Data bus for x8
– No Connect for x8
These pins should be left unconnected.
No Function for x8
These pins should be left unconnected
I/O Data Input/Output: Data bus for x4
– No Connect for x4
These pins should be left unconnected.
No Function for x4
These pins should be left unconnected
I/O
–
Supply
Supply
Data Strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data. It is used to capture data. For
the x16, LDQS is DQS for DQ0–DQ7 and UDQS is DQS for DQ8–DQ15. Pin 16 is
NU on x4 and x8.
Do Not Use: Must float to minimize noise on VREF.
DQ Power Supply: +2.5 ±0.2V (+2.6V ±0.1V for DDR400). Isolated on the die
for improved noise immunity.
DQ Ground. Isolated on the die for improved noise immunity.
Supply
Supply
Supply
Power Supply: +2.5V ±0.2V (+2.6V ±0.1V for DDR400).
Ground.
SSTL_2 reference voltage.
Table 2: Reserved NC Balls and Pins
TSOP
Numbers
Symbol
Type Description1
42,17
A12, A13
I Address inputs A12 and A13 for 256Mb, 512Mb and 1Gb devices. DNU for
FBGA.
NOTE:
1. NC balls/pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC
pins deemed to be of importance.
PDF: 09005aef816fd013/Source: 09005aef816ce127
128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT46V16M8.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT46V16M16 | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | Micron Technology |
| MT46V16M8 | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | Micron Technology |
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