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PDF CYP32G0401DX Data sheet ( Hoja de datos )
| Número de pieza | CYP32G0401DX | |
| Descripción | Multi-Gigabit Multi-Mode Quad HOTLINK Transceiver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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.com CYP32G0401DXPRELIMINARY
Multi-eGeitg4aUbit Multi-Mode Quad HOTLink-III™ TransceiverFeatures
Sh• Third-generation HOTLink® technology
ta• 2488- to 3125-Mbps signaling rate per serial link
a• XAUI/10G Ethernet compatible mode
.D• InfiniBand™ compatible
• Programmable 8-bit or 10-bit SERDES
w• Selectable 8B/10B encoding/decoding
w• Ethernet PCS functions using the IEEE802.3z ordered
w set state machine
m• Programmable receive framer provides alignment to
— A1/A2: SONET/SDH
o— 8B/10B COMMA: Ethernet, InfiniBand, XAUI
.c• Synchronous SSTL_2 parallel input/output interface
• Internal PLLs with no external PLL components
• Differential CML serial inputs per channel
U• Differential CML serial outputs per channel
— Source matched for 50Ω transmission lines
t4— No external bias resistors required
• Compatible with
e— Fiber-optic modules
e— Copper cables
— Circuit board traces
h• Diagnostic loop back and line loop back
• Signal detect input
S• Low Power (2.5W typical)
ta— Single +2.5V VDD supply
• 256-ball Thermally Enhanced BGA
• Commercial temperature range 0°C to +70°C
.Da• Industrial temperature range –40°C to +85°C
Functional Description
The CYP32G0401DX Quad HOTLink-III™ Transceiver is a
point-to-point communications building block allowing the
transfer of data over high-speed serial links (optical fiber, bal-
anced, and unbalanced copper transmission lines) at signaling
speeds ranging from 2488 to 3125 Mbps per serial link.
Each transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. Each receive channel accepts serial data and
converts it to parallel data, decodes the data into characters,
and presents these characters to an output register. Figure 1
illustrates typical connections between independent host sys-
tems and corresponding CYP32G0401DX parts. As a third-
generation HOTLink transceiver, the CYP32G0401DX ex-
tends the HOTLink family with enhanced levels of integration,
multi-gigabit data rates, and multi-mode versatility.
The transmit section of the CYP32G0401DX Quad HOTLink-
III shown in Figure 2 consists of four channels. Each channel
can accept either 8-bit data characters or pre-encoded 10-bit
transmission characters. Data characters are passed from the
Transmit Input Register to an embedded bypassable 8B/10B
Encoder to improve their serial transmission characteristics.
These encoded characters are then serialized and output from
Current Mode Logic (CML) differential transmission-line driv-
ers at a bit-rate which is a multiple of the input reference clock.
The receive section of the CYP32G0401DX Quad HOTLink-III
consists of four channels. Each channel accepts a serial bit-
stream from a CML differential line receiver and, using a com-
pletely integrated PLL Clock Synchronizer, recovers the timing
information necessary for data reconstruction. Each recov-
ered bit-stream is deserialized and framed into characters,
8B/10B decoded, and checked for transmission errors. Recov-
ered decoded characters are then written to an internal Elas-
ticity Buffer, and presented to the destination host system. The
integrated 8B/10B encoder/decoder may be bypassed for sys-
tems that present externally encoded or scrambled data at the
parallel interface.
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t4U10
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.Data10
Serial Links
CYP32G0401DX
Serial Links
Serial Links
CYP32G0401DX
Serial Links
Backplane or
Cabled
Connections
Figure 1. HOTLink-III™ System Connections
10
10
10
10
10
10
10
10
wwwCypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-02019 Rev. *C
Revised November 7, 2001
1 page  
PRELIMINARY
CYP32G0401DX
Pin Configuration (Bottom View)
20 19 18 17 16 15 14 13 12
11 10 9 8
7
65 4
3
2
1
DGND
DGND DGND RXCLKb RXD7b RCLKINb TXD4b DGND GTXCLKb TCLKOUT DGND DGND TXD5c GTXCLKc RXCLKc RXD2c RCLKINc DGND DGND
DGND A
DGND
DVDD DVDD RXD4b RXD6b RXDVb TXD5b TXD2b TXD0b VDIGCc TXENc TXD7c TXD3c TXD1c RXD0c RXD3c RXD5c DVDD DVDD
DGND B
DGND
DVDD DVDD RXD3b RXD5b TXENb TXD7b TXD3b TXD1b TSYNC TXERc TXD6c TXD2c COLc RXD1c RXD4c RXD7c DVDD DVDD
DGND C
RXD0b RXD1b RXD2b DVDD RXERb TXERb DVDD TXD6b GDIGCb GDIGCc DVDD TXD4c TXD0c DVDD
CRSc RXD6c DVDD RXERc RXDVc
OOFd D
RXCLKa OOFa CRSb COLb
OOFc RXDVd RXD7d RXCLKd E
RXD7a RXERa RXDVa OOFb
RXERd RXD6d RXD5d RXD4d F
RXD3a RXD4a RXD6a GDIGCa
GDIGCd RXD3d RXD2d RCLKINd G
RCLKINa CRSa RXD2a RXD5a
COLd
RXD1d RXD0d
DGND H
DGND
COLa RXD0a RXD1a
CRSd TXD0d TXD1d GTXCLKd J
DGND GTXCLKa TXD0a DVDD
TXD2d TXD3d TXD4d
TXD5d K
TXD1a TXD2a TXD3a TXD4a
VDIGCd TXD6d TXD7d
DGND L
TXD5a TXD6a TXD7a TXENa
TXERd DVDD TXENd
DGND M
DGND VDIGCa TXERa MDIO
FRSYN0 FRSYN1 TEST RESETN N
VDIGCb MDC VRXMb AVDD
AVDD GTXMc ANTEST1 ANTEST0 P
TMS
TCK
TRS VTXMb
GTXMd VRXMc VTXMc
REFP R
TDO
TDI GTXMb GRXMa
VRXMd VTXMd GRXMc
REFN
T
GRXMb LBEN VRXMa AVDD GTXMa GRXDa AVDD TXPa TXNa
VTXDb GTXDc TXPd TXNd AVDD GRXDd LOSd AVDD FRAME ENCODE GRXMd U
AGND
AVDD AVDD POLa LOSb VRXDa GRXDb GTXDa TXNb
TXPb
TXPc TXNc GTXDd GRXDc POLd LOSc SER8_10 AVDD
AVDD
AGND V
AGND
AVDD AVDD VTXMa RXPa RXNa VRXDb VTXDa GTXDb
VFS2
GFS1 VTXDc GFS3 VTXDd RXPd RXNd VRXDd AVDD
AVDD
AGND W
AGND
AGND AGND LOSa POLb RXPb RXNb GFS2 AGND
AGND VFS1 VFS3 AGND RXPc
RXNc VRXDc POLc AGND AGND
AGND Y
Document #: 38-02019 Rev. *C
Page 5 of 34
5 Page 
PRELIMINARY
CYP32G0401DX
CYP32G0401DX Receiver Pins (76)[2] (continued)
Pin Name
Level
I/O
Description
Y6 RXNc
CML
input
Channel c serial receive data, ext. ac coupled, int. bias. RXNc is
the negative differential input pin of the channel c Line Receiver.
The RXPc and RXNc look like a differential amplifier with each of
the input pins connected to VDD/2 through a 150Ω resistor. When
inputs are differentially terminated with a 150Ω resistor, the line
termination is nominally 100Ω. See Figure 6.
V5 LOSc
LVPECL input
Channel c receive loss of signal indicate. The signal input on the
LOSc pin may come from a fiber module and indicates if there is
a Loss of Signal (LOS) condition. If a LOS condition occurs, the
data input is squelched and no data is sent to the data recovery
block. When no data edges are present at the inputs to the clock
recovery Digital Phase-Locked Loop (DPLL), its output frequency
will be locked to the frequency of the transmit Frequency Synthe-
sizer. The polarity of the LOSc signal is controlled by the POLc pin
as shown in Table 4.
Y4 POLc
SSTL_2 input
Channel c receive loss of signal polarity. The POLc pin controls
the polarity of the LOSc signal as shown in Table 4.
H2, H3
G2, G3
F1, F2
F3, E2
RXD0d, RXD1d
RXD2d, RXD3d
RXD4d, RXD5d
RXD6d, RXD7d
SSTL_2
outputs Channel d receive data. The receive data RXDd[7:0] are clocked
out of the Elasticity FIFO by RCLKINd.
F4 RXERd
SSTL_2
output
Channel d receive error (RXERd) in MODE 1
Channel d receive data bit9 (RXD9d) in MODE 2
Channel d receive invalid character flag (ERRd) in MODE 3
Not used in MODE 4
E3 RXDVd
SSTL_2
output
Channel d receive data valid (RXDVd) in MODE 1
Channel d receive data bit8 (RXD8d) in MODE 2
Channel d receive code-group select (RXKd) in MODE 3
Not used in MODE 4
J4 CRSd
SSTL_2
output
Channel d receive carrier sense indicate (CRSd) in MODE 1
Not used in MODE 2
Channel d receive idle code (IDLEd) in MODE 3
Channel d receive frame pulse flag (FRPd) in MODE 4
H4 COLd
SSTL_2
output
Channel d receive collision indicate (COLd) in MODE 1
Not used in MODE 2
Channel d receive invalid character flag (ERRd) in MODE 3
Not used in MODE 4
E1 RXCLKd
SSTL_2
output
Channel d receive clock output reference. The RXCLKd pin out-
puts either a buffered RCLKINd, or the recovered clock. This is
determined by the status of LBEN on the rising edge of RESETN
as follows: LBEN = 0 selects the buffered RCLKINd; LBEN = 1
selects the recovered clock.
D1 OOFd
SSTL_2 input
Not used in MODE 1
Not used in MODE 2
Not used in MODE 3
Channel d OOF indicate in MODE 4
G1 RCLKINd
SSTL_2 input
Channel d receive Elasticity FIFO output clock. RCLKINd clocks
the receive data RXDd[7:0], RXDVd, and RXERd out of the chan-
nel d Elasticity FIFO.
W6 RXPd
CML
input
Channel d serial receive data, ext. ac coupled, int. bias. RXPd is
the positive differential input pin of the channel d Line Receiver.
The RXPd and RXNd look like a differential amplifier with each of
the input pins connected to VDD/2 through a 150Ω resistor. When
inputs are differentially terminated with a 150Ω resistor, the line
termination is nominally 100Ω. See Figure 6.
Document #: 38-02019 Rev. *C
Page 11 of 34
11 Page | ||
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