|
|
PDF CYP25G01K100 Data sheet ( Hoja de datos )
| Número de pieza | CYP25G01K100 | |
| Descripción | 2.5Gbps Programmable Serial Interface | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CYP25G01K100 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Sheet4U.com2.5-Gbps Programmable Serial Interface™Features
ta• High-speed (HS) Programmable Serial Interface™
a(PSI™)
.D• 2.48- to 2.5-Gbps serial signaling rate
w• Full Bellcore and ITU jitter compliance
w• Flexible parallel-to-serial conversion in transmit path
w • Flexible serial-to-parallel conversion in receive path
• Multiple selectable loopback/loop-through modes
m• 100K of usable gates of CPLD logic
o• 240K of integrated memory
— 192K of synchronous or asynchronous SRAM
.c— 48K of true Dual-Port or FIFO RAM
• Internal transmit and receive phase-locked loops
(PLLs)
U• Logic dedicated Spread Aware PLL
t4• Transmit FIFO for flexible variable phase clocking
• Differential CML serial input with internal termination
and DC-restoration
e• Differential CML serial output with source-matched
impedance of 50Ω
e• 240 user-programmable I/Os
• Any Volt™ I/O interface
h— Programmable as 1.5V, 1.8V, 2.5V, 3.3V
• Multiple I/O standards
S— LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II),
taHSTL(I-IV), and GTL+
— Fully PCI-compliant (Rev. 2.2)
a• Direct interface to standard fiber-optic modules
• Designed to drive:
— Fiberoptic modules
.D— Copper cables
2.5-Gbps PSI Family—Standards Supported
— Circuit board traces
— Backplane links
— Box-to-box links
— Chip-to-chip communication
• Extremely flexible clocking options
— Four global clocks
— Up to 192 additional product term clocks
— Clock polarity at every register
• Carry chain logic for fast and efficient arithmetic
operations
• JTAG programming interface with boundary scan
support
• Power-saving mode
• Supported standards:
— SONET OC-48 and SDH STM-16
— InfiniBand™
— Custom 2.5-Gbps interface
Development Software
• Warp®
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine
editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows® 9x, 2000, NT 4.0, XP, and ME
— Supports all Cypress programmable logic products
wSONET/SDH
wHigh Speed
PSI Device
CYS25G01K100
CYP25G01K100
SONET/SDH (OC48/STM16)
X
InfiniBand
X
Custom
X
X
w om2.5-Gbps PSI Family—General Features
U.cDevice
Typical
Gates Macrocells
t425G01K100 46K–144K 1536
Cluster
Memory
(Kbits)
192
Channel
Memory
(Kbits)
48
Maximum User-
Programmable I/O
Package Offering
240 456-BGA (35 × 35 mm, 1.27-mm pitch)
ee2.5-Gbps PSI Family—Performance
taShDevice
Channels and Link Speed Total Bandwidth
a25G01K100
1 × 2.5 Gbps
2.5 Gbps
.DNote:
1. See the section titled Switching Characteristics for definition.
fMAX2(Logic)[1] (MHz)
222
Logic Speed—
tPD Pin-to-Pin[1] (ns)
7.5
wwCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
wDocument #: 38-02021 Rev. *C
Revised December 4, 2002
1 page  
2.5-Gbps Programmable Serial Interface
Clock Inputs
GCLK[1:0], RXCLK and TXCLK
4
L o g ic
B lo ck
0
36
16
L o g ic
36 Block
16 7
L o g ic
B lo ck
1
36
16
L o g ic
36 Block
6
16
L o g ic
B lo ck
2
36
16
PIM
L o g ic
36 Block
5
16
L o g ic
B lo ck
3
36
16
L o g ic
36 Block
4
16
C lu s te r
M em ory
0
25
8
C lu ste r
25 Memory
1
8
CC = Carry Chain
64 Inputs From
Horizontal Routing
Channel
144 Outputs to
64 Inputs From
Vertical Routing
Channel
Horizontal and Vertical
cluster-to-channel PIMs
Figure 5. PSI Logic Block Cluster Diagram
Logic Block
The LB is the basic building block of the programmable logic
block of the PSI architecture. It consists of a product term
array, an intelligent product-term allocator, and 16 macrocells.
Product Term Array
Each LB features a 72 × 83 programmable product term array.
This array accepts 36 inputs from the PIM. These inputs
originate from device pins and macrocell feedbacks as well as
cluster memory and channel memory feedbacks. Active LOW
and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 83 product
terms in the array can be created from any of the 72 inputs.
Of the 83 product terms, 80 are for general-purpose use for
the 16 macrocells in the LB. Two of the remaining three
product terms in the LB are used as asynchronous set and
asynchronous reset product terms. The final product term is
the Product Term clock (PTCLK) and is shared by all 16
macrocells within an LB.
Product Term Allocator
Through the product term allocator, Warp software automati-
cally distributes the 80 product terms as needed among the 16
macrocells in the LB. The product term allocator provides two
important capabilities without affecting performance: product
term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On PSI devices, product
terms are steered on an individual basis. Any number between
1and 16 product terms can be steered to any macrocell.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one function has one or more product terms in its equation that
are common to other functions, those product terms are only
created once. The PSI product term allocator allows sharing
across groups of four macrocells in a variable fashion. The
software automatically takes advantage of this capability so
that the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All
steering and sharing configurations have been incorporated in
the timing specifications for the PSI devices.
.
Document #: 38-02021 Rev. *C
Page 5 of 44
5 Page 
2.5-Gbps Programmable Serial Interface
Clock Tree Distribution
The global clock tree performs two primary functions. First, the
clock tree generates the four internal global clocks by multi-
plexing four reference clocks derived from the Transceiver
Blocks and from the package pins and four PLL driven clocks.
Second, the clock tree distributes the four global clocks to
every cluster, channel memory, I/O block, and datapath cell on
the die. The global clock tree is designed such that the clock
skew is minimized while maintaining an acceptable clock
delay.
Spread Aware™ PLL
The 2.5-Gbps PSI device features an on-chip PLL designed
using Spread Aware™ technology for low EMI applications. In
general, PLLs are used to implement time-division-multiplex
circuits to achieve higher performance with fewer device
resources.
For example, a system that operates on a 32-bit data path that
runs at 40 MHz can be implemented with 16-bit circuitry that
runs internally at 80 MHz. PLLs can also be used to take
advantage of the positioning of the internally generated clock
edges to shift performance towards improved setup, hold or
clock-to-out times.
There are several frequency multiply (X1, X2, X3, X4, X5, X6,
X8, X16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options
available to create a wide range of clock frequencies from a
single clock input (GCLK[0]). For increased flexibility, there are
seven phase shifting options which allow clock skew/de-skew
by 45°, 90°, 135°, 180°, 225°, 270°, or 315°.
The Spread Aware feature refers to the ability of the PLL to
track a spread-spectrum input clock such that its spread is
seen on the output clock with the PLL staying locked. The total
amount of spread on the input clock should be limited to 0.6%
of the fundamental frequency. Spread Aware feature is
supported only with X1, X2 and X4 multiply options.
The Voltage Controlled Oscillator (VCO), the core of the PSI
PLL is designed to operate within the frequency range of 100
MHz to 266 MHz. Hence, the multiply option combined with
input (GCLK[0]) frequency should be selected such that this
VCO operating frequency requirement is met. This is demon-
strated in Table 3 (columns 1, 2, and 3).
Another feature of this PLL is the ability to drive the output
clock (INTCLK) off the PSI chip to clock other devices on the
board, as shown in Figure 11 below. This off-chip clock is half
the frequency of the output clock as it has to go through a
register (I/O register or a macrocell register).
This PLL can also be used for board deskewing purpose by
driving a PLL output clock off-chip, routing it to the other
devices on the board and feeding it back to the PLL’s external
feedback input (GCLK[1]). When this feature is used, only
limited multiply, divide and phase shift options can be used.
Table 3 describes the valid multiply and divide options that can
be used without an external feedback. Table 4 describes the
valid multiply and divide options that can be used with an ex-
ternal feedback.
Table 5 describes the valid phase shift options that can be
used with or without an external feedback.
Table 6 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to VCO output and not to the divided output.
o ff-c h ip s ig n a l (e x te rn a l fe e d b a c k )
IN T C L K 0 , IN T C L K 1 , IN T C L K 2 , IN T C L K 3
A n y R e g is te r
G CLK1
N o rm a l I/O s ig n a l p a th
S e n d a g lo b a l
c lo c k o ff c h ip
L o c k D e te c t/IO p in
2
C
C lo c k T re e
D e la y
fb fb
Lock
C lk 0 0
C lk 4 5 0
G C L K 0 S ource
C lo c k
C lk 9 0 0
C lk 1 3 5 0
C lk 1 8 0 0
C lk 2 2 5 0
C lk 2 7 0 0
PLL
C lk 3 1 5 0
X 1, X 2, X 3, X 4, X 5,
X6, X8, X16
P h a s e s e le c tio n
P h a s e s e le c tio n
P h a s e s e le c tio n
D iv id e
÷ 1 -6 ,8 ,1 6
D iv id e
÷ 1 -6 ,8,1 6
D iv id e
÷ 1 -6 ,8 ,1 6
P h a s e s e le c tio n
D iv id e
÷ 1 -6 ,8,1 6
C
G C LK0
2
C
G CLK1
2
C
TX C LK
2
C
IN T C L K 0
IN T C L K 1
IN T C L K 2
R X C LK
2
C
IN T C L K 3
Figure 11. Block Diagram of Spread Aware PLL for CYP25G01K100
Document #: 38-02021 Rev. *C
Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYP25G01K100.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CYP25G01K100 | (CYPxxx) Programmable Serial Interface | Cypress Semiconductor |
| CYP25G01K100 | (CYPxxx) Programmable Serial Interface | Cypress Semiconductor |
| CYP25G01K100 | 2.5Gbps Programmable Serial Interface | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |