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PDF CYP15G0401DXA Data sheet ( Hoja de datos )
| Número de pieza | CYP15G0401DXA | |
| Descripción | Quad HOTLink II Transceiver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYP15G0401DXA
Quad HOTLink II™ Transceiver
Features
• 2nd generation HOTLink® technology
• Fibre Channel and Gigabit Ethernet compliant 8B/10B-
coded or 10-bit unencoded
• 8-bit encoded data transport
• 10-bit unencoded data transport
• Selectable parity check/generate
• Selectable multi-channel bonding options
— Four 8-bit channels
— Two 16-bit channels
— One 32-bit channel
— N x 32-bit channel support (inter-chip)
• Selectable input clocking options
• Selectable output clocking options
• MultiFrame™ receive framer provides alignment to
— Bit, byte, half-word, word, multi-word
— COMMA or Full K28.5 detect
— Single or Multi-byte framer for byte alignment
— Low-latency option
• Skew alignment support for multiple bytes of offset
• Synchronous LVTTL parallel input interface
• Synchronous LVTTL parallel output interface
• 200-to-1500 MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs per
channel
• Dual differential PECL-compatible serial outputs per
channel
— Source matched for 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Compatible with
— fiber-optic modules
— copper cables
— circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
— Frequency range detect
• Low Power (2.8W typical)
— Single +3.3V VCC supply
• 256-ball Thermally Enhanced BGA
• 0.25µ BiCMOS technology
Functional Description
The CYP15G0401DXA Quad HOTLink II™ Transceiver is a
point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 200-to-1500 MBaud
per serial link. The multiple channels in each device may be
combined to allow transport of wide buses across significant
distances with minimal concern for offsets in clock phase or
link delay.
Each transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. Each receive channel accepts serial data and
converts it to parallel data, decodes the data into characters,
and presents these characters to an output register. Figure 1
illustrates typical connections between independent host sys-
tems and corresponding CYP15G0401DXA parts. As a sec-
ond-generation HOTLink device, the CYP15G0401DXA ex-
tends the HOTLink family with enhanced levels of integration
and faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices.
10
10
10
10
10
10
10
10
Serial Links
Serial Links
Serial Links
Serial Links
Backplane or
Cabled
Connections
Figure 1. HOTLink II™ System Connections
10
10
10
10
10
10
10
10
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-02002 Rev. *B
Revised July 10, 2001
1 page  
PRELIMINARY
CYP15G0401DXA
Pin Configuration (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
INC1-
OUT
C1−
INC2-
OUT
C2−
VCC
IND1-
OUT
D1−
GND IND2-
OUT
D2−
INA1-
OUT
A1−
GND INA2-
OUT
A2−
VCC
INB1-
OUT
B1−
INB2-
OUT
B2−
B
INC1+
OUT
C1+
INC2+
OUT
C2+
VCC IND1+
OUT
D1+
GND IND2+
OUT
D2+
INA1+
OUT
A1+
GND INA2+
OUT
A2+
VCC INB1+
OUT
B1+
INB2+
OUT
B2+
C
TDI
TMS INSELC INSELB VCC
PAR
CTL
SDA
SEL
GND
BOE[7] BOE[5] BOE[3] BOE[1]
GND
TX
MODE
RX
MODE
VCC
TX
RATE
RX
RATE
LPEN
TDO
[0] [0]
D
TCLK
TRSTZ INSELD INSELA VCC
RF
MODE
SPD
SEL
GND
BOE[6] BOE[4] BOE[2] BOE[0]
GND
TX
MODE
RX
MODE
VCC
BOND
INH
RXLE
RFEN
MAS
TER
[1] [1]
E VCC VCC VCC VCC
VCC VCC VCC VCC
F
TX
PERC
TX
OPC
TX
DC[0]
RXCK
SEL
BISTLE RX RXOPB RX
STB[1]
STB[0]
G
TX
DC[7]
TXCK
SEL
TX
DC[4]
TX
DC[1]
DEC OELE
MODE
FRAM
CHAR
RX
DB[1]
H GND GND GND GND
GND GND GND GND
J
TX TX
CTC[1] DC[5]
TX
DC[2]
TX
DC[3]
K
RX RXCLK TX
DC[2]
C– CTC[0]
LFIC
L
RX RXCLK TX
DC[3] C+ CLKC
TX
DC[6]
M
RX
DC[4]
RX
DC[5]
RX
DC[7]
RX
DC[6]
RX
STB[2]
RX
DB[0]
RX
DB[5]
RX
DB[2]
RX
DB[3]
RX
DB[4]
RX
DB[7]
RX
CLK
B+
RX
DB[6]
LFIB
RX TX
CLK DB[6]
B−
TX TX TX
CTB[1] CTB[0] DB[7]
TX
CLKB
N GND GND GND GND
GND GND GND GND
P
RX
DC[1]
RX RX RX
DC[0] STC[0] STC[1]
R
RX
STC[2]
RX
OPC
TX
PERD
TX
OPD
TX
DB[5]
TX
DB[4]
TX
DB[3]
TX
DB[2]
TX
DB[1]
TX
DB[0]
TX
OPB
TX
PERB
T VCC VCC VCC VCC
VCC VCC VCC VCC
U
TX
DD[0]
TX
DD[1]
TX
DD[2]
TX
CTD[1]
VCC
RX
DD[2]
RX
DD[1]
GND
RX
OPD
BOND
_ALL
−REF
CLK
TXDA[1]
GND
TXDA[4]
TX
CTA[0]
VCC
RX RXOPA RX
RX
DA[2]
STA[2] STA[1]
V
TX
DD[3]
TX TX RX
DD[4] CTD[0] DD[6]
VCC
RX
DD[3]
RX
STD[0]
GND
RX
STD[2]
BOND
ST[0]
+REF
CLK
BOND
ST[1]
GND TXDA[3] TXDA[7]
VCC
RX
DA[7]
RX
DA[3]
RX
DA[0]
RX
STA[0]
W
TX
DD[5]
TX
DD[7]
LFID
RXCLK
D–
VCC
RX
DD[4]
RX
STD[1]
GND
TX
CLK
TXRST TXOPA SCSEL GND TXDA[2] TXDA[6] VCC
LFIA
RX RX RX
CLK DA[4] DA[1]
O− A−
Y
TX
DD[6]
TX
CLKD
RX
DD[7]
RXCLK
D+
VCC
RX
DD[5]
RX
DD[0]
GND
TX
CLK
N/C
TX
CLKA
TX
PERA
GND TXDA[0] TXDA[5] VCC
TX
CTA[1]
RX
CLK
RX
DA[6]
RX
DA[5]
O+ A+
Document #: 38-02002 Rev. *B
Page 5 of 48
5 Page 
PRELIMINARY
CYP15G0401DXA
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
Device Control Signals
PARCTL
3-Level Select[2] Parity Check/Generate Control. Used to control the different parity check and generate
Static Control Input functions.
When LOW, parity checking is disabled, and the RXOPx outputs are all disabled
(High-Z).
When MID, and the encoder/decoder are enabled (TXMODE[1] ≠ L, RXMODE[1] ≠ L),
TXDx[7:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity
is generated for the RXDx[7:0] outputs and presented on RXOPx. When the encoder
and decoder are disabled (TXMODE[1] = L, RXMODE[1] = L), theTXDx[7:0] and
TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity
is generated for the RXDx[7:0] and RXSTx[1:0] outputs and presented on RXOPx.
SPDSEL
3-Level Select[2],
static configuration
input
When HIGH, the and the encoder/decoder are enabled (TXMODE[1] ≠ L,
RXMODE[1] ≠ L), the TXDx[7:0] and TXCTx[1:0] inputs are checked (along with
TXOPx) for valid ODD parity, and ODD parity is generated for the RXDx[7:0] and
RXSTx[2:0] outputs and presented on RXOPx. When the encoder is and decoder are
disabled (TXMODE[1] = L, RXMODE[1] = L), theTXDx[7:0] and TXCTx[1:0] inputs are
checked (along with TXOPx) for valid ODD parity, and ODD parity is generated for the
RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx.
Serial Rate Select. This input specifies the operating bit-rate range of both transmit and
receive PLLs. LOW = 200–400 MBd, MID = 400–800 MBd, HIGH = 800–1500 MBd.
REFCLK±
Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and
or single-ended
receive PLLs. This input clock may also be selected to clock the transmit and receive
LVTTL input clock parallel interfaces. For an LVCMOS or LVTTL input clock, connect REFCLK+ to the
reference clock and leave REFCLK– open. For an LVPECL differential clock, both inputs
must be connected.
When TXCKSEL = LOW, REFCLK is used as the clock for the parallel transmit data
(input) interface.
When RXCKSEL = LOW, REFCLK is used as the clock for the parallel receive data
(output) interface.
Analog I/O and Control
OUTA1±
OUTB1±
OUTC1±
OUTD1±
CML Differential
Output
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V
referenced) are capable of driving terminated transmission lines or standard fiber-optic
transmitter modules. These outputs must be AC-coupled for PECL-compatible connec-
tions.
OUTA2±
OUTB2±
OUTC2±
OUTD2±
CML Differential
Output
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compati-
ble connections.
INA1±
INB1±
INC1±
IND1±
LVPECL Differential Primary Differential Serial Data Inputs. These inputs accept the serial data stream for
Input
deserialization and decoding. The INx1± serial streams are passed to the receiver Clock
and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.
INA2±
INB2±
INC2±
IND2±
LVPECL Differential Secondary Differential Serial Data Inputs. These inputs accept the serial data stream
Input
for deserialization and decoding. The INx2± serial streams are passed to the receiver
Clock and Data Recovery (CDR) circuits to extract the data content when
INSELx = LOW.
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous
Receive Input Selector. Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the INx1± input is selected.
When LOW, the INx2± input is selected.
Document #: 38-02002 Rev. *B
Page 11 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYP15G0401DXA.PDF ] | |
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