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PDF CYP25G02K200 Data sheet ( Hoja de datos )
| Número de pieza | CYP25G02K200 | |
| Descripción | (CYPxxx) Programmable Serial Interface | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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.com Programm(HaigbhleSSpeerieadl IDnetevrifcaecse)PRELIMINARY
Sheet4U Programmable BandwidthFeatures
ta• 200 Mbps – 1.5 Gbps, 2.5 Gbps serial signaling rate
a• Flexible parallel-to-serial conversion in transmit path
.D• Flexible serial-to-parallel conversion in receive path
w• Multiple selectable loopback/loop-through modes
w• 100K to 200K usable gates of CPLD logic
w • 240K to 480 Kb of integrated memory
— 192K to 384Kb of synchronous or asynchronous
mSRAM
o— 48K to 96Kb of true Dual-Port or FIFO RAM
• Internal transmit and receive PLLs
.c• Logic dedicated Spread Aware PLL
• Transmit FIFO for flexible variable phase clocking
• Differential CML serial input with internal termination
Uand DC-restoration
t4• Differential CML serial output with source matched im-
pedance of 50Ω
• 160–240 user programmable I/Os
e• Any Volt™ I/O interface
— Programmable as 1.8V, 2.5V, 3.3V
e• Multiple I/O standards
h— LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II),
HSTL(I-IV), and GTL+
S• Direct interface to standard fiber-optic modules
• Designed to drive:
ta— Fiberoptic Modules
— Copper Cables
a— Circuit Board Traces
— Backplane Links
.D— Box-to-Box Links
— Chip-to-Chip Communication
w• Extremely flexible clocking options
— Four global clocks
w— Up to 192 additional product term clocks
— Clock polarity at every register
w om• Carry chain logic for fast and efficient arithmetic
.coperations
• Fully PCI compliant (Rev. 2.2)
U• JTAG programming interface with boundary scan sup-
t4port
e• High-Speed (HS) or Frequency Agile (FA) Programma-
eble Serial Interface™ (PSI™) versions available
hHigh-Speed PSI Features
taS• 2.5 Gbps/channel serial signaling rate
a• Full Bellcore and ITU jitter compliance
.DNote:
1. For more detail, refer to the “Frequency Agile PSI” data sheet.
• Power-saving mode
• Up to two serial channels available to allow:
— High-Bandwidth
— Redundancy
• Supported standards:
— InfiniBand™
— SONET OC-48
Frequency Agile PSI Features[1]
• 200 Mbps–1.5 Gbps serial signaling rate per channel
• Up to eight serial channels available to allow:
— Frequency Agile
— Redundancy
• Selectable input and output clocking options
• MultiFrame™ receive framer provides alignment to:
— Bit, byte, half-word, word, multi-word
— COMMA or Full K28.5 detect
— Single or Multi-byte framer for byte alignment
— Low-latency option
• Skew alignment support for multiple bytes of offset
• Selectable parity check/generate
• Serial Built-In-Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
— Frequency range detect
• Supported standards:
— Fibre Channel
— Gigabit Ethernet
— ESCON
— DVB
— SMPTE
Development Software
• Warp®
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine
editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows® 95, 98 & NT for $99
— Supports all Cypress programmable logic products
wwCypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
wDocument #: 38-02021 Rev. *B
Revised August 31, 2001
1 page  
Programmable Serial Interface
PRELIMINARY (High Speed Devices)
Functional Description
Global Routing Description
The Programmable Serial Interface (PSI) family is a point-to-
point or point-to-multipoint programmable communications
building block allowing the manipulation and transfer of data
over high-speed serial links at signaling speeds ranging from
200 Mbps to 1.5Gbps or 2.5 Gbps per serial link. The PSI
family is designed to combine the high speed, predictable tim-
ing, high density, low power, and ease of use of complex pro-
grammable logic devices (CPLD) with the serializing/deserial-
izing (SERDES) capability of high-speed serial transceivers.
The family is divided into two groups: High-Speed PSI and
Frequency—Agile PSI. Both groups have unique transceiver
characteristics that define the specific transceiver block oper-
ation of a given PSI device.
The architecture of the device is based on logic block clusters
(LBC) and serial transceiver blocks that are connected by hor-
izontal and vertical routing channels. Each LBC features eight
individual logic blocks (LB) of 16 marcrocells and two cluster
memory blocks. Adjacent to each LBC is a channel memory
block which is externally accessible through the I/O interface.
Each transmit channel of the transceiver accepts parallel char-
acters, encodes each character for transport and converts it to
serial data. Each receive channel accepts serial data and con-
verts it to parallel data, decoding the data into characters and
presents these characters to the routing channels of the PSI
unit.
High-Speed PSI
The routing architecture in the PLD block of a PSI device is
made up of horizontal and vertical (H&V) routing channels.
These routing channels allow signals to move among I/Os,
logic blocks and memories. In addition to the horizontal and
vertical routing channels that interconnect the I/O banks,
channel memory blocks, transceiver blocks and logic block
clusters, each LBC contains a Programmable Interconnect
Matrix™ (PIM™), which is used to route signals among the
logic blocks and the cluster memory blocks in the LBC.
Figure 5 is a block diagram of the routing channels that inter-
face within the PSI architecture. The LBC is exactly the same
for every member of the PSI family.
Transceiver Block
Each transceiver block of a given PSI device will have one
serializer transmit path and one deserializer receive path op-
erating at a speed from 200 Mbps to 1.5Gbps or 2.5 Gbps. The
transceiver block interfaces to the routing channels of the PSI
device through highly configurable datapath cells. For specific
architecture and operation of the transceiver blocks please re-
fer to the Serial Transceiver Operation section (page 17).
High-Speed PSI Transceiver Blocks
High-Speed PSI devices include one or two transceiver blocks
operating at 2.5 Gbps per channel. Both channels operate in-
dependently of each other. They use the same reference
clock.
The transceiver operation of the high-speed programmable
serial interface devices is self-contained in a single block. It
has separate transmit and receive PLLs and a Clock and Data
Recovery (CDR) unit for flexible clocking. The transmit chan-
nel accepts a 16-bit input character from the routing channels
and passes the character to an elasticity buffer. This character
is then serialized and output on dual differential transmission-
line drivers at the required bit-rate. The receive channel ac-
cepts a serial bit-stream from the two differential line receivers.
This bit-stream is deserialized and a 16-bit character is pre-
sented to the routing channels in the PSI device. The block
also features loop-back and loop-through modes for simplified
design debugging.
The internal interfacing to the transceiver blocks of the high-
speed device occur through the port definition of the high-
speed transceiver block. The internal signals and their defini-
tion are described in the “Pin & Signal Description” section
(page 46).
Standard Datapath Cell
Figure 4 is a block diagram of the PSI datapath cell. The data-
path cell contains a three-state transmit buffer, a receive buff-
er, and a register that can be configured as an transmit or
receive register.
The Transceiver Enable (TE) can be selected from one of the
four global control signals or from one of two Output Control
Channel (OCC) signals. The transmit enable can be config-
CY PSI
ured as always enabled or always disabled or it can be con-
trolled by one of the remaining inputs to the mux. The selection
is done via a mux that includes VCC and GND as inputs.
Programmable
Host Bus
Interface
REFCLK±
IN+
IN–
SD
OUT–
OUT+
+
–
Optical
Transceiver
Serial Data
Serial Data
RD+
RD–
SD
TD–
TD+
One of the global clocks can be selected as the clock for the
datapath cell register. The clock mux output is an input to a
clock polarity mux that allows the transmit/receive register to
be clocked on either edge of the clock.
Optical
Fiber Links
Figure 3. High-Speed PSI System Connections with an Optical
Interface.
Document #: 38-02021 Rev. *B
Page 5 of 58
5 Page 
Programmable Serial Interface
PRELIMINARY (High Speed Devices)
I/O Banks
The PSI interfaces the horizontal and vertical routing channels
to the pins through I/O banks. There are several I/O banks per
device as shown in Figure 10 and all I/Os from an I/O bank are
located in the same section of a package for PCB layout con-
venience. There exist two kinds of I/O banks; fixed-signal I/O
banks and user programmable I/O banks.
The first fixed signal bank is the Serial Signal Bank. This bank
includes all differential serial data transmission and receive
signals. The second bank is the Transceiver Control Bank.
This bank includes all static signal pins required for the config-
uration and operation of the transceiver blocks in each of the
PSI devices.
Each PSI device has several types of user programmable I/O
banks. The table on the following page indicates the availabil-
ity of each type of programmable bank by device. Supported
I/O standards for each bank are addressed by the appropriate
VREF and VCCIO voltages. All the VREF and VCCIO pins in an
I/O bank must be connected to the same VREF and VCCIO volt-
age respectively. This requirement restricts the number of I/O
standards supported by an I/O bank at any given time. It also
dictates the I/O standard used for the GCTL[3:0] pins.
The architecture defining each programmable I/O bank con-
sists of several I/O cells, where each I/O cell contains an in-
put/output register, an output enable register, programmable
slew rate control and programmable bus hold control logic.
Each I/O cell drives a pin output of the device; the cell also
supplies an input to the device that connects to a dedicated
track in the associated routing channel.
There are four dedicated inputs (GCTL[3:0]) that are used as
Global Control Signals available to every I/O cell. These global
control signals may be used as output enables, register resets
and register clock enables as shown in Figure 11.
I/O Bank I/O Bank I/O Bank
PSI Programmable I/O Banks
Device
25G01K100
Flexible
Semi-
Specific
Flexible VCCIO VREF
Bank[0:3, 5] Bank[4]
Bank[6:7]
VCCIO=3.3V 1.5V 0.68-0.90V
25G02K100 Bank[0:3] Bank[4]
Bank[5:7]
VCCIO=3.3V 1.5V 0.68-0.90V
IO Standards
I/O
Standard
VREF (V)
Min Max
LVTTL
N/A
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
0.9 1.1
SSTL3 I
1.3 1.7
SSTL3 II
1.3 1.7
SSTL2 I
1.15 1.35
SSTL2 II
1.15 1.35
HSTL I
0.68 0.9
HSTL II
0.68 0.9
HSTL III
0.68 0.9
HSTL IV
0.68 0.9
Termination
VCCIO Voltage (VTT)
3.3 V
3.3 V
3.0 V
2.5 V
1.8 V
3.3 V
N/A
3.3 V
3.3 V
2.5 V
2.5 V
1.5 V
1.5 V
1.5 V
1.5 V
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
1.25
1.25
0.75
0.75
1.5
1.5
PSI
I/O Bank I/O Bank I/O Bank
Figure 10. PSI I/O Bank Block Diagram.
Document #: 38-02021 Rev. *B
Page 11 of 58
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYP25G02K200.PDF ] | |
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