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PDF BT457 Data sheet ( Hoja de datos )
| Número de pieza | BT457 | |
| Descripción | (BT457 / BT458) Monolithic CMOS 256 Color Palette RAMDAC | |
| Fabricantes | Conexant Systems | |
| Logotipo |  |
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B1R2At.5MD4MaD5tHAa7zSC/1h/B3e5ettM44UH5.zc8/o16m5 MHz Monolithic CMOS 256 Color PaletteThe Bt457 and Bt458 are pin- and software-compatible RAMDACs designed specifically
wfor high-performance, high-resolution color graphics. The architecture enables a display
wof 1280 x 1024 bit-mapped color graphics (up to 8 bits per pixel plus up to 2 bits of
w overlay information). This minimizes the use of costly ECL interfacing, because most of
mthe high-speed (pixel clock) logic is contained on-chip. The multiple pixel ports and
internal multiplexing enable TTL-compatible interface (up to 32 MHz) to the frame
obuffer, while maintaining the 165 MHz video data rates required for sophisticated color
graphics.
.cThe Bt457 is a single-channel version of the Bt458 and has a 256 x 8 color lookup
table with a single 8-bit video D/A converter. It includes a PLL output to enable subpixel
synchronization of multiple Bt457s.
UOn-chip features include programmable blink rates, bit plane masking and blinking,
t4color overlay capability, and a dual-port color palette RAM.
Distinguishing Features
• 165, 135, 125, 110, 80 MHz
operation
• 4:1 or 5:1 input mux
• 256-word dual-port color palette
• Four dual-port overlay registers
• RS-343A-compatible outputs
• Bit plane read and blink masks
• Standard MPU interface
• 84-pin PLCC or PGA package
• +5 V CMOS monolithic
construction
Applications
• High-resolution color graphics
e • CAE/CAD/CAM
eFunctional Block Diagram
• Image processing
• Video reconstruction
ShCLOCK* CLOCK
VAA
GND
FSADJUST VREF
ataLD*
.DP[7:0] 40
(A-E)
wOL[1,0] 10
w(A-E)
SYNC*
mBLANK*
w t4U.coCLOCK
Load
Control
MUX
Control
40 40
8
Blink
Control
8
Latch
Latch
10 10
MUX
Read Blink
Mask Mask
22
256 X 12
(24)
Color
Palette
4(8)
4(8)
4 x 12
(24)
Overlay
4(8)
Bus Control
ADDR Reg
8
RG
B
4(8)
eeCE* R/W CO C1
D[7:0]
COMP
IOR (N/C)
IOG (IOUT)
IOB (PLL)
www.DataShData Sheet
L45801 Rev. N
September 2, 1999
1 page  
Bt457/Bt458
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
List of Figures
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 3-1.
Figure 3-2.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Bt457/Bt458 84-Pin J-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Bt457/Bt458 84-Pin PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Video Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Composite Video Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Sample Layout Showing Power and Ground Plane Isolation Gaps . . . . . . . . . . . . . . . . . . . 3-2
Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Generating the Bt458 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Generating the Bt457 Signals (Monochrome Application). . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Generating the Bt457 Clock Signals (Color Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Video Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
MPU Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
84-Pin Plastic J-Lead (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
84-Pin Ceramic PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
L45801 Rev. N
Conexant
v
5 Page 
Bt457/Bt458
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
1.0 Circuit Description
1.2 Pin Descriptions
1.2 Pin Descriptions
Table 1-1. Pin Descriptions (1 of 2)
Pin Name
Description
BLANK*
SYNC*
LD*
P[7:0]
{A–E}
OL[1,0]
{A–E}
Composite blank control input (TTL compatible). A logical 0 drives the analog outputs to the blanking level, as
specified in Table 1-5. BLANK* is latched on the rising edge of LD*. When BLANK* is a logical 0, the pixel and
overlay inputs are ignored.
Composite sync control input (TTL compatible). A logical 0 on this input switches off a 40 IRE current source on
the IOG output (see Figure 1-4). SYNC* does not override any other control or data input, as illustrated in
Table 1-5; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of
LD*.
If sync information is not generated on the IOG output, this pin should be connected to GND.
Load control input (TTL compatible). The P[7:0] {A–E}, OL[1,0] {A–E}, BLANK*, and SYNC* inputs are latched on
the rising edge of LD*. While LD* is either one fourth or one fifth the CLOCK rate, it can be phase independent of
the CLOCK and CLOCK* inputs. LD* can have any duty cycle within the limits specified in the AC Characteristics
section.
Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which of the 256 entries
in the color palette RAM is used to provide color information. Either 4 or 5 consecutive pixels (up to 8 bits per
pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected
to GND.
The {A} pixel is output first, followed by the {B} pixel, then the {C} pixel, etc., until all 4 or 5 pixels have been
output, at which point the cycle repeats.
Overlay select inputs (TTL compatible). These control inputs are latched on the rising edge of LD*. In conjunction
with bit 6 of the command register, they specify which palette is to be used for color information, as follows:
IOR, IOG,
IOB, IOUT
OL1 OL0
00
01
10
11
CR6 = 1
Color Palette RAM
Overlay Color 1
Overlay Color 2
Overlay Color 3
CR6 = 0
Overlay Color 0
Overlay Color 1
Overlay Color 2
Overlay Color 3
When accessing the overlay palette, the P[7:0] {A–E} inputs are ignored. Overlay information bits (up to 2 bits per
pixel) for either 4 or 5 consecutive pixels are input through this port. Unused inputs should be connected to GND.
Red, green, and blue video current outputs. These high-impedance current sources can directly drive a doubly
terminated 75 Ω coaxial cable (see Figure 3-2). The Bt457 outputs IOUT rather than IOR, IOG, and IOB.
L45801 Rev. N
Conexant
1-3
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BT457.PDF ] | |
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