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PDF PKD01 Data sheet ( Hoja de datos )
| Número de pieza | PKD01 | |
| Descripción | Monolithic Peak Detector with Reset-and-Hold Mode | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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aheet4U.com wMitohnRoelistheitc-aPneda-kHoDPledKtDMe0co1tdoerFEATURES
SMonolithic Design for Reliability and Low Cost
taHigh Slew Rate: 0.5 V/s
aLow Droop Rate
.DTA = 25؇C: 0.1 mV/ms
TA = 125؇C: 10 mV/ms
wLow Zero-Scale Error: 4 mV
wDigitally Selected Hold and Reset Modes
w Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
mUncommitted Comparator On-Chip
oAvailable in Die Form
t4U.cGENERAL DESCRIPTION
eThe PKD01 tracks an analog input signal until a maximum
eamplitude is reached. The maximum value is then retained as a
peak voltage on a hold capacitor. Being a monolithic circuit, the
hPKD01 offers significant performance and package density
advantages over hybrid modules and discrete designs without
Ssacrificing system versatility. The matching characteristics
attained in a monolithic circuit provide inherent advantages
tawhen charge injection and droop rate error reduction are
primary goals.
aInnovative design techniques maximize the advantages of mono-
lithic technology. Transconductance (gm) amplifiers were chosen
over conventional voltage amplifier circuit building blocks. The
.Dgm amplifiers simplify internal frequency compensation, minimize
acquisition time and maximize circuit accuracy. Their outputs
are easily switched by low glitch current steering circuits. The
wsteered outputs are clamped to reduce charge injection errors
upon entering the hold mode or exiting the reset mode. The inher-
wently low zero-scale error is further reduced by active Zener-Zap
mtrimming to optimize overall accuracy.
FUNCTIONAL BLOCK DIAGRAM
+IN –IN
OUTPUT V+
V–
LOGIC
GND
DET
–IN
+IN
–IN
+IN
RST
–
CMP
+
GATED
"gm"
– AMP
A
+
GATED
"gm"
– AMP
B
+
V–
OUTPUT
BUFFER
–
D1 C
+
PKD01
OUTPUT
RST
0
0
1
1
DET
0
1
1
0
OPERATIONAL MODE
PEAK DETECT
PEAK HOLD
RESET
INDETERMINATE
CH
SWITCHES SHOWN FOR:
RST = “0,” DET = “0”
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A bias
current cancellation circuit minimizes droop error at high ambi-
ent temperatures.
Through the DET control pin, new peaks may either be detected
or ignored. Detected peaks are presented as positive output
levels. Positive or negative peaks may be detected without
additional active circuits, since Amplifier A can operate as an
inverting or noninverting gain stage.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
w ataSheet4U.coREV. A
.DInformation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
wuse, nor for any infringements of patents or other rights of third parties
wwhich may result from its use. No license is granted by implication or
wotherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
PKD01
WAFER TEST LIMITS (@ VS = ؎15 V, CH = 1000 pF, TA = 25؇C, unless otherwise noted.)
Parameter
Symbol Conditions
PKD01N
Limit
Unit
“gm” AMPLIFIERS A, B
Zero-Scale Error
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range1
Feedthrough Error
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain1
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range1
Low Output Voltage
“OFF” Output Leakage Current
Output Short-Circuit Current
VZS
VOS
IB
IOS
AV
CMRR
PSRR
VCM
RL = 10 kΩ, VO = ± 10 V
–10 V ≤ VCM ≤ +10 V
± 9 V ≤ VS ≤ ± 18 V
∆VIN = 20 V, DET = 1, RST = 0
VOS
IB
IOS
AV
CMRR
PSRR
VCM
VOL
IL
ISC
2 kΩ Pull-Up Resistor to 5 V
–10 V ≤ VCM ≤ +10 V
± 9 V ≤ VS ≤ ± 18 V
ISINK ≤ 5 mA, Logic GND = 5 V
VOUT = 5 V
VOUT = 5 V
7
6
250
75
10
74
76
± 11.5
66
3
1000
300
3.5
82
76
± 11.5
0.4
–0.2
80
45
7
mV max
mV max
nA max
nA max
V/mV min
dB min
dB min
V min
dB min
mV max
nA max
nA max
V/mV min
dB min
dB min
V min
V max
V min
µA max
mA min
mA min
DIGITAL INPUTS–RST, DET2
Logic “1” Input Voltage
Logic “0” Input Voltage
Logic “1” Input Current
Logic “0” Input Current
MISCELLANEOUS
Droop Rate3
Output Voltage Swing Amplifier C
Short-Circuit Current Amplifier C
Power Supply Current
gm AMPLIFIERS A, B
Slew Rate
Acquisition Time1
COMPARATOR
Response Time
VH
VL
IINH
IINL
VDR
VOP
ISC
ISY
SR
tA
tA
VH = 3.5 V
VL = 0.4 V
TJ = 25°C,
TA = 25°C
RL = 2.5 kΩ
No Load
2
0.8
1
10
0.1
0.20
± 11
40
7
9
0.1% Accuracy, 20 V Step, AVCL = 1
0.01% Accuracy, 20 V Step, AVCL = 1
5 mV Overdrive, 2 kΩ Pull-Up Resistor to 5 V
0.5
41
45
150
V min
V max
µA max
µA max
mV/ms max
mV/ms max
V min
mA max
mA min
mA max
V/µs
µs
µs
ns
MISCELLANEOUS
Switch Aperture Time
Switching Time
Buffer Slew Rate
tAP
tS
SR RL = 2.5 kΩ
75 ns
50 ns
2.5 V/µs
NOTES
1Guaranteed by design.
2DET = 1, RST = 0.
3Due to limited production test times, the droop current corresponds to junction temperature (T J). The droop current vs. time (after power-on) curve clarifies this
point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A) also. The warmed-up (TA) droop current
specification is correlated to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.
Ambient (TA) temperature specifications are not subject to production testing.
REV. A
–5–
5 Page 
THEORY OF OPERATION
The typical peak detector uses voltage amplifiers and a diode or
an emitter follower to charge the hold capacitor, CH, indirect-
ionally (see Figure 1). The output impedance of A plus D1’s
dynamic impedance, rd, make up the resistance which deter-
mines the feedback loop pole. The dynamic impedance is
rd
=
kT
qId
,
where
Id
is
the
capacitor
charging
current.
The pole moves toward the origin of the S plane as Id goes to
zero. The pole movement in itself will not significantly lengthen
the acquisition time since the pole is enclosed in the system
feedback loop.
VIN
INPUT
VOUT (A) = V IN (A) ؋ AV (A)
A
VOUT
+
ROUT
D1
rd
VH
CH
C
OUTPUT
Figure 1. Conventional Voltage Amplifier Peak Detector
When the moving pole is considered with the typical frequency
compensation of voltage amplifiers however, there is a loop stability
problem. The necessary compensation can increase the required
acquisition time. ADI’s approach replaces the input voltage ampli-
fier with a transconductance amplifier (see Figure 2).
The PKD01 transfer function can be reduced to:
VOUT = 1 ≈ 1
VIN 1 + sCH + 1
1 + sCH
gm gm ROUT
gm
where: gm Ϸ 1 µA/mV, ROUT Ϸ 20 MΩ.
The diode in series with A’s output (see Figure 2) has no effect
because it is a resistance in series with a current source. In
addition to simplifying the system compensation, the input
transconductance amplifier output current is switched by cur-
rent steering. The steered output is clamped to reduce and match
any charge injection.
VIN
INPUT
IOUT (A) = V IN (A) ؋ gm (A)
IOUT
A
D1 VH
ROUT
CH
C OUTPUT
VOUT
Figure 2. Transconductance Amplifier Peak Detector
Figure 3 shows a simplified schematic of the reset gm amplifier,
B. In the track mode, Q1 and Q4 are ON and Q2 and Q3 are
OFF. A current of 2I passes through D1, I is summed at B and
passes through Q1, and is summed with gmVIN. The current sink
can absorb only 3I, thus the current passing through D2 can
PKD01
only be: 2K – gm VIN. The net current into the hold capacitor
node then, is gmVIN [IH = 2I – (2I – gmVIN)]. In the hold mode,
Q2 and Q3 are ON while Q1 and Q4 are OFF. The net current
into the top of D1 is –I until D3 turns ON. With Q1 OFF, the
bottom of D2 is pulled up with a current I until D4 turns ON,
thus, D1 and D2 are reverse biased by <0.6 V, and charge injec-
tion is independent of input level.
The monolithic layout results in points A and B having equal
nodal capacitance. In addition, matched diodes D1 and D2 have
equal diffusion capacitance. When the transconductance ampli-
fier outputs are switched open, points A and B are ramped
equally, but in opposite phase. Diode clamps D3 and D4 cause
the swings to have equal amplitudes. The net charge injection
(voltage change) at node C is therefore zero.
V+
I 2I
A
D1
C
D2
B
D3
C
D4
CH
6
Q1 Q2
Q3 Q4
A
LOGIC
VIN gm V IN
B CONTROL
3I 3I A > B = PEAK DETECT
V– A < B = PEAK HOLD
Figure 3. Transconductance Amplifier with Low Glitch
Current Switch
The peak transconductance amplifier, A is shown in Figure 4.
Unidirectional hold capacitor charging requires diode D1 to be
connected in series with the output. Upon entering the peak
hold mode D1 is reverse-biased. The voltage clamp limits charge
injection to approximately 1 pC and the hold step to 0.6 mV.
Minimizing acquisition time dictates a small CH capacitance. A
1000 pF value was selected. Droop rate was also minimized by
providing the output buffer with an FET input stage. A cur-
rent cancellation circuit further reduces droop current and
minimizes the gate current’s tendency to double for every 10°
temperature change.
V+
I 2I
D3
D1
D2 rd
D4
C
CH
6
Q1 Q2
Q3 Q4
A
LOGIC
VIN gm V IN
B CONTROL
3I 3I A > B = PEAK DETECT
V– A < B = PEAK HOLD
Figure 4. Peak Detecting Transconductance Amplifier
with Switched Output
REV. A
–11–
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet PKD01.PDF ] | |
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