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PDF LM4560 Data sheet ( Hoja de datos )
| Número de pieza | LM4560 | |
| Descripción | Advanced PCI Audio Accelerator | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LM4560 (archivo pdf) en la parte inferior de esta página. Total 54 Páginas | ||
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December 1998
LM4560
Advanced PCI Audio Accelerator
General Description
LM4560 is an advanced PCI audio accelerator providing full
legacy compatibility, wavetable synthesis, DirectMusic, Di-
rectSound, and DirectSound3D on a single chip for the high-
performance, cost-sensitive consumer market. It supports
Sound Blaster functionality and is fully PC98 compliant.
The LM4560 integrates a 64-voice wave table engine with
per voice effect processing capability. It supports the upcom-
ing Microsoft™ DirectMusic API and is fully compatible with
DLS Level 1 (downloadable samples) specification. The
LM4560 is optimized for Microsoft Windows™ 98 and Win-
dows NT5.0 WDM streaming architecture with re-routable
end-point support. The LM4560 includes DirectSound3D ac-
celeration hardware for ITD (Interaural Time Difference), IID
(Interaural Intensity Difference), Pan, Delay, and Doppler
hardware.
The LM4560 supports Sound Blaster Pro/16 DOS games
while improving gaming audio quality. The LM4560 supports
both the legacy analog gameport and a Digital Enhanced
Game Port. When coupled with DirectInput™ driver, the Digi-
tal Enhanced Game Port can save up to 12% of the CPU
overhead nominally required by a conventional analog game
port. The LM4560 employs a high precision 26-bit digital
mixer, providing an accurate 20-bit output and higher than 90
dB signal-to-noise ratio when used with high quality AC97
Rev 1.03 and Rev 2.0 codecs.
The LM4560 is designed with aggressive power manage-
ment. It is PCI Bus Power Management Interface (PPMI
1.0)-compliant. The LM4560 supports multiple Rev 2.0 AC97
codecs, which are useful for notebook docking systems.
With a low power, 3.3V process and a space conscious 100
TQFP package, the LM4560 is also well suited for Notebook
systems.
In summary, the LM4560 provides a balanced combination
of features and performance to the end-user. By combining
PCI bus mastering for DirectSound acceleration, Hardware
Wave table synthesizer, Digital Enhanced Game Port and
DirectSound 3D audio acceleration. It delivers high perfor-
mance, high quality audio, high-end features with efficient
power management in a space-efficient 100 TQFP package.
Features
n PCI 2.1-compliant with Bus Mastering optimized for
multiple stream operation
n On-chip per voice cache minimizes PCI bandwidth
n Up to 20X improvement over ISA DMA on PCI bus
bandwidth utilization
Advanced Wavetable Synthesizer
n Wavetable synthesis with 64-voices polyphony, which
supports all combinations of stereo/mono, 8-/16-bits,
and signed/unsigned samples
n Per channel volume, pitch shift, left/right pan, tremolo,
vibrato and envelope control (32 channels in hardware)
n Per channel effect process ing and effect volume control
for reverb, chorus, and echo
n DLS1-compliant Downloadable Samples support
Legacy Compatibility
n Legacy game audio support with SoundBlaster Pro/16
compatibility on the PCI bus
n Legacy DMA support on PCI Bus with DDMA-enabled or
standard (non-DDMA) PCI chipsets
n FM through realtime FM-to-wavetable conversion
n MPU-401 compatible UART for external or internal
synthesis
n General MIDI/GS command interpretation for wavetable
& effect synthesis
High Quality Audio and AC97 Support
n CD quality audio with higher than 90 dB signal-to-noise
ratio using an external high quality AC97 codec
n AC97 support with full duplex, independent sample rate
converter for audio recording and playback
n On-chip sample rate converter ensures all internal
operation at 48 kHz
n High precision internal 26-bit digital mixer with 16- and
20-bit digital audio output
Advanced Streaming Architecture
n Microsoft WDM Streaming architecture compliant and
“Re-routable endpoint” support
n Three stereo capture channels
n AC97 stereo recording channel through AC-link
DirectSound 3D
n 64-voices DirectSound channels
n 32-voices DirectSound3D accelerator with IID, ITD, and
Doppler effects on 3D positional audio buffers
n DirectSound accelerator for volume, pan, and pitch shift
control on streaming or static buffers
Telephony & Modem
n Full duplex speaker phone with AC97 2.0 audio-modem
codec
n Fax-modem with host based software
Extras
n Fully Plug and Play PCI controller and software
n Digital Enhanced Game port enables an analog joystick
to emulate digital joystick performance using the
National Semiconductor-provided DirectInput driver. This
eliminates up to 12% CPU overhead wasted on joystick
polling.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Microsoft™ is a trademark of Microsoft Corporation.
Windows® is a registered trademark of Microsoft Corporation.
DirectInput™ is a trademark of Microsoft Corporation
© 1998 National Semiconductor Corporation DS100910
www.national.com
1 page  
1.0 Pin Description (Continued)
1.2 PIN DESCRIPTION
Symbol Pin(s) Type
Description
VDD 20, 39, IN 3.3V Power Supply
52, 53,
69, 83,
100
VSS 11, 30, IN Ground
48, 60,
75, 90
PCI BUS INTERFACE SIGNALS (51)
AD[31:0]
92–99, I/O PCI Address/Data Bus.
3–10,
A time-multiplexed
21–28,
address data bus.
31–38
C/BE[3:0]
1, 12,
19, 29
I/O PCI Command/Byte
Enable. Defines the type
of AD bus transaction
type.
FRAME
13 I/O Cycle Frame. A PCI
transaction begins and
ends with the FRAME
signal.
IRDY
14 I/O Initiator Ready. An active
low indicates the cycle
initiator is ready to send
or receive data.
TRDY
15 I/O Target Ready. An active
low indicates that the
target is read to complete
the current transaction.
DEVSEL
16 I/O Device Select. An active
low indicates the target
has decoded its address.
STOP
17 I/O STOP. An active low
indicates the target wants
the initiator to stop data
during the current data
phase.
PAR
18 I/O Parity. Generates an
even parity for the
AD[31.0].
RST
86 IN Reset. A low active signal
which resets the PCI
device.
INT 84 OUT Interrupt. An active low
signals in interrupt to the
CPU.
PCICLK
87 IN Clock. The clock that
drives the PCI timing.
GNT
88 IN Grant. An active low
signals the master has
access to the PCI bus.
REQ
89 OUT Request. An active low
indicates the master
wants access to the PCI
bus.
Symbol Pin(s) Type
Description
PCI BUS INTERFACE SIGNALS (51)
CLKRUN
85 I/O Clock Run. An active low
signal used for power
management on
motherboards only. It is
not assigned a pin on the
PCI connector.
PME
91 OUT Power Management
Event. An active low
signal used for power
management for add in
cards or motherboards. It
is assigned a pin on the
PCI connector.
TC 78 IN Terminal Count. This
input is asserted by the
DMA controller to indicate
the end of a DMA
transfer. The signal is
only effective during a
DMA access cycle.
IDSEL
2 IN Initialization Device
Select. An active high
allows reads to the PCI
devices configuration
registers.
MPU-401 INTERFACE SIGNALS (2)
MIDIOUT
50 OUT MIDI Data Out. Sends
midi data to the midi
connector.
MIDIIN
49 IN MIDI Data In. Receives
midi data from an
optocoupler.
AC97 CODEC INTERFACE SIGNALS (6)
ACRST
57 OUT AC97 Master Reset. An
active low which resets
the internal circuitry of
AC97 codecs.
ACCLK
55 IN AC97 Bit Clock. A
12.288 MHz clock from
the codec. This is used to
synchronize the data
streams to and from the
codecs.
ACSYNC
56 I/O AC97 Sync. Used to start
the data frame used to
format the serial data to
and from the codecs.
ACDI1
58 IN Primary CODEC Serial
Data Input. This receives
serial data in from the
primary codec.
ACDI2
59 IN Secondary CODEC
Serial Data Input. This
receives serial data in
from the secondary
codec.
5 www.national.com
5 Page 
3.0 Register Description (Continued)
IO Offset
B0h
B4h
B8h
BCh
C0h
C4h
C8H
CCh
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
+3h
MISCINT
START_B
STOP_B
CSPF_B
SBDMAL
SCE2R
STIMER
LFO_CTRL_B
ST_TARGET
RSVD
AINT_B
AINTEN_B
CSO
CPTR + LBA
ESO
LFO_CTRL
GVSEL + PAN
EBUF1
EBUF2
RSVD
CSO
CPTR + LBA
ESO
ATTRIBUTE
GVSEL + PAN
RSVD
RSVD
RSVD
+2h +1h
RSVD
LFO_CT_B
SBDMAC
SBDD
RSVD + I2S_DELTA
Bank A: Channel Register
ARAM_A (CIR<32)
FMS+ALPHA(11:8)
LFO_CT
VOL
DELTA
FMC+RVOL[6:1]
CTRL + Ec(11:8)
Bank B: Channel Register
ARAM_B (CIR>=32)
FMS+ALPHA(11:8)
ERAM_B (CIR>=32)
LFO_INIT(Bank A)
DELTA
FMC+RVOL[6:1]
CTRL + VOL(11:8)
+0h
SBCTRL
ALPHA(7:0)
RVOL[0]+CVOL
Ec(7:0)
ALPHA(7:0)
RVOL[0]+CVOL
VOL(7:0)
3.1.1.15 I/O Access Mode:
3.1.1.15.1 Audio I/O Base:
The Audio Processor requires a 256-byte PCI I/O space. The
base address (called the Audio I/O Base) resides in PCI
Configuration Register 10h.
All audio processor registers (00h–FFh) can be accessed by
host in an I/O cycle with address: Audio I/O Base+offset.
There are 4 byte registers in ADLIB I/O Base. Physically,
those registers are alaised to Audio Base Reg10h–13h.
3.1.1.15.4 Legacy Gameport I/O Base:
If CFG_REG44h[4] is ‘0’, Gameport I/O Base is 200h; if
CFG_REG44h[4] is ‘1’, Gameport I/O Base is 208h.
There are 8 byte registers in Gameport I/O Base. Physically,
those registers are identical to Audio Base Reg30h–37h.
3.1.1.15.2 Legacy SB I/O Base:
If CFG_REG44h[0] is ‘0’, SB I/O Base is 220h; if
CFG_REG44h[0] is ‘1’, SB I/O Base is 240h.
There are 16 byte registers in SB I/O Base. Physically, those
registers are aliased to Audio Base Reg10h–1Fh.
3.1.1.15.3 Legacy ADLIB I/O Base:
If CFG_REG44h[2] is ‘0’, ADLIB I/O Base is 388h; if
CFG_REG44h[2] is ‘1’, ADLIB I/O Base is 38Ch.
3.1.1.15.5 Legacy MPU401 I/O Base:
Controlled by CFG_REG44h[6], Audio Processor response
to either of two legacy MPU401 I/O address spaces. If
CFG_REG44h[6] is ‘0’, MPU401 I/O Base is 330h; if
CFG_REG44h[6] is ‘1’, MPU401 I/O Base is 300h.
There are 4 byte registers in MPU401 I/O Base. Physically,
those registers are identical to Audio Base Reg20h–23h.
11 www.national.com
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| PDF Descargar | [ Datasheet LM4560.PDF ] | |
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