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PDF LM4550 Data sheet ( Hoja de datos )
| Número de pieza | LM4550 | |
| Descripción | AC 97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier/ Sample Rate Conversion and National 3D Sound | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 2002
LM4550
AC ’97 Rev 2.1 Multi-Channel Audio Codec with Stereo
Headphone Amplifier, Sample Rate Conversion and
National 3D Sound
General Description
The LM4550 is an audio codec for PC systems which is fully
PC99 compliant and performs the analog intensive functions
of the AC97 Rev2.1 architecture. Using 18-bit Sigma-Delta
A/D’s and D/A’s, the LM4550 provides 90 dB of Dynamic
Range.
The LM4550 was designed specifically to provide a high
quality audio path and provide all analog functionality in a PC
audio system. It features full duplex stereo A/D’s and D/A’s
and an analog mixer with 4 stereo and 3 mono inputs, each
of which has separate gain, attenuation and mute control.
The LM4550 provides a stereo headphone amplifier with an
independent gain control and also supports National’s 3D
Sound stereo enhancement and variable sample rate con-
version. The sample rate for the A/D and D/A can be pro-
grammed separately with a resolution of 1 Hz to convert any
rate between 4 kHz–48 kHz.
The LM4550 features the ability to connect several codecs
together in a system to provide up to six channels for sur-
round sound applications. Multiple codec systems can be
built using the standard AC-Link format of one serial data
stream per codec, or using a unique National Semiconductor
feature for chaining codecs together. This chain feature re-
quires only a single data stream to the controller.
The AC97 architecture separates the analog and digital func-
tions of the PC audio system allowing both for system design
flexibility and increased performance.
Key Specifications
n Analog Mixer Dynamic Range
n D/A Dynamic Range
n A/D Dynamic Range
n Headphone Amp THD+N at 50 mW
into 32Ω
97dB (typ)
89dB (typ)
90dB (typ)
0.02% (typ)
Features
n AC’97 Rev 2.1 compliant
n Several LM4550s can be combined together for up to 6
channel operation
n Unique National chaining function allows multiple codecs
to be connected serially and use only a single controller
SDATA_IN pin
n High quality Sample Rate Conversion (SRC) from 4 kHz
to 48 kHz in 1 Hz increments.
n Stereo headphone amp with separate gain control
n National’s 3D Sound circuitry
n External Amplifier Power Down (EAPD) control from
codec
n PC-Beep passthrough to Line Out while reset is held
active low
n Digital 3.3V and 5V compliant
Applications
n Desktop PC audio systems on PCI cards, AMR cards, or
with motherboard chips sets featuring AC-Link
n Portable PC systems as on MDC cards, or with a
chipset or accelerator featuring AC-Link
n 2, 4, or 6 channel systems
© 2002 National Semiconductor Corporation DS100972
www.national.com
1 page  
Electrical Characteristics(Notes 1, 3) The following specifications apply for AVDD = 5V, DVDD = 5V, Fs =
48kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless
otherwise specified. (Continued)
Symbol
Parameter
Conditions
TFALL
TRST_LOW
TRST2CLK
TSH
TSYNC2CLK
TSU2RST
TRST2HZ
Fall Time
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
RESET# active low pulse width
For cold reset
RESET# inactive to BIT_CLK start up For cold reset
SYNC active high pulse width
For warm reset
SYNC inactive to BIT_CLK start up For warm reset
Setup to trailing edge of RESET#
For ATE Test Mode
Rising edge of RESET# to Hi-Z
For ATE Test Mode
LM4550
Typical Limit
(Note 7) (Note 8)
Units
(Limits)
6 nS (max)
1.0 µS (min)
162.8 nS (min)
1.3 µS
162.8 nS (min)
15 nS (min)
25 nS (max)
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: These specifications are guaranteed by design and characterization; they are not production tested.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum
allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4550, TJMAX = 150˚C.
The typical junction-to-ambient thermal resistance is 74˚C/W for package number VBH48A.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Machine Model, 220 pF–240 pF discharged through all pins.
Note 7: Typicals are measured at 25˚C and represent the parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
5 www.national.com
5 Page 
Pin Descriptions (Continued)
Name
XTL_IN
Pin
2
XTL_OUT
3
SDATA_OUT
5
BIT_CLK
6
SDATA_IN
SYNC
RESET#
8
10
11
ID0 45
ID1 46
EAPD
47
CHAIN_IN
48
I/O
I
O
I
I/O
O
I
I
I
I
O
I
DIGITAL I/O AND CLOCKING
Functional Description
24.576 MHz crystal input. Use a fundamental-mode type crystal. When operating from a
crystal, a 1MΩ resistor must be connected across pins 2 and 3.
24.576 MHz crystal output. When operating from a crystal, a 1MΩ resistor must be connected
across pins 2 and 3.
This data stream contains both control data and DAC audio data. This input is sampled by
the LM4550 on the falling edge of BIT_CLK.
OUTPUT when in Primary Codec Mode: This pin outputs a 12.288 MHz clock which is
derived (internally divided by two) from the 24.576MHz crystal input (XTL_IN).
INPUT when in Secondary Codec Mode (Multiple Codec configurations only): 12.288MHz
clock is to be supplied from an external source, such as from the BIT_CLK of a Primary
Codec.
This data stream contains both control data and ADC audio data. This output is clocked out
by the LM4550 on the rising edge of BIT_CLK.
48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT
serial streams. SYNC must be synchronous to BIT_CLK.
This active low signal causes a hardware reset which returns the control registers to their
default conditions.
ID0 and ID1 set the codec address for multiple codec use where ID0 is the LSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default to
Primary codec setting (same as connecting both pins to DVdd). These pins are of inverted
polarity relative to their internal ID0, ID1 registers. If pin 45 is connected to GND, then ID0 will
be set to "1" internally. Connection to DVdd corresponds to a "0" internally.
ID0 and ID1 set the codec address for multiple codec use where ID1 is the MSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default to
Primary codec setting (same as connecting both pins to DVdd). These pins are of inverted
polarity relative to their internal ID0, ID1 registers. If pin46 is connected to GND, then ID1 will
be set to "1" internally. Connection to DVdd corresponds to a "0" internally.
The contents of "Powerdown Ctrl/Stat" register 26h bit 15 determines the logic level output on
this pin. This pin is to be connected to an external power amplifier’s shutdown pin. The output
voltage is set by the digital supply. If EAPD=0, then a logic low is output and the external
amplifer is enabled. If EAPD=1, the amplifer is shutdown. Power up default is EAPD=0.
By setting the two LSBs of register 74h to something other than the codec ID, the codec
stops sending its own SDATA_IN signal and instead passes the signal connected here out the
SDATA_IN pin. This pin can be left floating if no software will use register 74h and the chain
feature is not used. When the chain feature is used, another codec’s SDATA_IN pin should
be connected here, or else this pin should be grounded to prevent the possibility of floating
the SDATA_IN signal at the controller.
POWER SUPPLIES AND REFERENCES
Name
Pin I / O
Functional Description
AVDD
25 I Analog supply.
AVSS
26 I Analog ground.
DVDD 1,9 I Digital supply.
DVSS
4,7 I Digital ground.
VREF
Nominal 2.2V reference output. Not intended to sink or source current. Bypassing of this pin
27 O
should be done with short traces to maximize performance.
VREFOUT
28
Nominal 2.2V reference output. Can source up to 5mA of current and can be used to bias a
O
microphone.
AFILT1
This pin is not used and should be left open (NC). However, a capacitor to ground on this pin
29 O
is permitted - it will not affect performance.
11 www.national.com
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet LM4550.PDF ] | |
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