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PDF CY2037 Data sheet ( Hoja de datos )
| Número de pieza | CY2037 | |
| Descripción | High Accuracy EPROM Programmable PLL Die for Crystal Oscillators | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY2037
High Accuracy EPROM Programmable
PLL Die for Crystal Oscillators
Features
Benefits
• EPROM-programmable die for in-package programming of Enables quick turnaround of custom oscillators
crystal oscillators
Lowers inventory costs through stocking of blank parts
• High resolution PLL with 12 bit multiplier and 10 bit divider Enables synthesis of highly accurate and stable output clock
frequencies with zero or low PPM
• EPROM-programmable capacitor tuning array
• Twice programmable die
Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal
Enables reprogramming of programmed part, to correct errors,
and control excess inventory
• Simple 4-wire programming interface
Enables programming of output frequency after packaging
• On-chip oscillator runs from 10–30 MHz crystal
Lowers cost of oscillator as PLL can be programmed to a high
frequency using a low-frequency, low-cost crystal
• EPROM-selectable TTL or CMOS duty cycle levels
Duty cycle centered at 1.5V or VDD/2
Provides flexibility to service most TTL or CMOS applications
• Operating frequency
— 1–200 MHz at 5V
— 1–100 MHz at 3.3V
— 1–66.67 MHz at 2.7V
Services most PC, networking, and consumer applications
• Sixteen selectable post-divide options, using either PLL or Provides flexibility in output configurations and testing
reference oscillator output
• Programmable PWR_DWN or OE pin
Enables low-power operation or output enable function
• Programmable asynchronous or synchronous OE and
PWR_DWN modes
Provides flexibility for system applications, through selectable
instantaneous or synchronous change in outputs
• Low Jitter outputs
— < ±100ps (pk-pk) at 5V
— < ±125ps (pk-pk) at 3.3V
Suitable for most PC, consumer, and networking applications
• 3.3V or 5V operation
Lowers inventory cost as same die services both applications
• Small Die
Enables encapsulation in small-size, surface mount packages
• Controlled rise and fall times and output slew rate
Has lower EMI than oscillators
CY2037 Logic Block Diagram
PWR_DWN
or OE
XG CRYSTAL
XD
OSCILLATOR
XD
HIGH
ACCURACY
PLL
Die Configuration
Top View
CONFIGURATION
EPROM
VDD
AVDD
XD
XD
N/C
XG
PWR_DWN
or OE
1
2
3
4
5
6
7
10 CLKOUT
9 AVSS
8 VSS
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
CLKOUT
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 24, 1997
1 page  
PRELIMINARY
CY2037
Output Clock Switching Characteristics Over the Operating Range
Symbol
Description
Test Conditions
Min Typ
Max
t1w Output Duty Cycle at 1–27 MHz, CL <= 50 pF
1.4V, VDD = 4.5–5.5V 27–80 MHz, CL <= 15pF
t1w = t1A ÷ t1B
27–125 MHz, CL <= 25pF
125–200 MHz, CL <= 15pF
45
45
40
40
t1x Output Duty Cycle at 1–66.6 MHz, CL <= 50 pF
VDD/2, VDD = 4.5–5.5V 66.6–125 MHz, CL <= 25 pF
t1x = t1A ÷ t1B
125–200 MHz, CL <= 15pF
45
40
40
t1y Output Duty Cycle at 1–50 MHz, CL <= 30 pF
VDD/2, VDD = 3.0–3.6 50–100 MHz, CL <= 15pF
t1y = t1A ÷ t1B
45
40
t1z Output Duty Cycle at 1–40 MHz, CL <= 15 pF
VDD/2, VDD = 2.7–3.6V 40–66.6 MHz, CL <= 15 pF
t1z = t1A ÷ t1B
45
40
t2 Output Clock Rise time Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 50 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 4.5V–5.5V, CL = 50 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF
t3 Output Clock Fall time Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 50 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 4.5V-5.5V, CL = 50 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF
t4
Start-up time out of
PWR_DWN or OE pin LOW to HIGH[2]
power-down
1
55
55
60
60
55
60
60
55
60
55
60
1.8
1.2
0.9
3.4
4.0
2.4
4.0
1.8
1.2
0.9
3.4
4.0
2.4
4.0
2
t5a Power Down delay time PWR_DWN pin HIGH to output LOW
(synchronous setting) (T=frequency oscillator period)
T/2 T+10
t5b Power Down delay time PWR_DWN pin HIGH to output LOW
(asynchronous setting)
t6 Power Up time
From power on[2]
t7a
Output disable time
OE pin HIGH to output Hi-Z
(synchronous setting) (T=frequency oscillator period)
10 15
12
T/2 T+10
t7b
Output disable time
OE pin HIGH to output Hi-Z
(asynchronous setting)
10 15
t8
Output enable time
PWR_DWN or OE pin LOW to HIGH
100
t9 Peak-to-Peak Period VDD= 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz
Jitter
VDD= 3.0V–3.6V, Fo > 33 MHz, VCO >100 MHz
VDD= 3.0V–5.5V, Fo <33 MHz
±50
±75
±100
±100
±125
±250
Note:
2. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
Unit
%
%
%
%
%
%
%
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ms
ns
ns
ns
ps
ps
ps
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CY2037.PDF ] | |
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