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PDF STLC7550 Data sheet ( Hoja de datos )
| Número de pieza | STLC7550 | |
| Descripción | LOW POWER LOW VOLTAGE ANALOG FRONT END | |
| Fabricantes | ST Microelectronics | |
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STLC7550
LOW POWER LOW VOLTAGE ANALOG FRONT END
. GENERAL PURPOSE SIGNAL PROCESSING
ANALOG FRONT END (AFE)
. TARGETED FOR V.34bis MODEM AND
56Kbps MODEM APPLICATIONS
. 16-BIT OVERSAMPLING Σ∆ A/D AND D/A
CONVERTERS
. 83dB SIGNAL TO NOISE RATIO FOR SAM-
PLING FREQUENCY UP TO 9.6kHz @ 3V
. 87dB DYNAMIC RANGE @ 3V
. FILTER BANDWIDTHS :
0.425 x THE SAMPLING FREQUENCY
. ON-CHIP REFERENCE VOLTAGE
. SINGLE POWER SUPPLY RANGE :
2.7 TO 5.5V
. LOW POWER CONSUMPTION LESS THAN
30mW OPERATING POWER 3V
. STAND-BY MODE POWER CONSUMPTION
LESS THAN 3µW at 3V
. PROGRAMMING SAMPLING FREQUENCY
. MAX. SAMPLING FREQUENCY : 45kHz
. SYNCHRONOUS SERIAL INTERFACE FOR
... PROCESSOR DATAS EXCHANGE. MASTER
OR SLAVE OPERATIONS
0.50µm CMOS PROCESS
TQFP44 PACKAGE
STLC7546 MODE OF OPERATION COMPATIBLE
Maximum Power Dissipation 30mW is well suited
for Battery operations.
In case of battery low, STLC7550 will continue to
work even at a 2.7V level.
STLC7550 also provides clock generator for all
sampling frequencies requested for V.34bis and
56Kbps applications.
This new AFE can also be used for PC mother
boards or add-on cards or stand alone MODEMs.
It can be used in a master mode or slave mode.
The slave mode eases multi AFE architecture de-
sign in saving external logical glue.
TQFP44 (10 x 10 x 1.40 mm)
(Full Plastic Quad Flat Pack)
ORDER CODE : STLC7550TQFP
DESCRIPTION
The STLC7550 is a single chip Analog Front-end
(AFE) designed to implement modems up to
56Kbps.
It has been especially designed for host processing
application in which the modulation software
(V.34bis, 56Kbps) is performed by the main applica-
tion processor : Pentium, Risc or DSP processors.
The main target of this device is stand alone appli-
ances as Hand Held PC (HPC), Personnal Digital
Assistants (PDA), Webphones, Network Comput-
ers, Set Top Boxes for Digital Television (Satellite
and Cable).
To comply with such applications STLC7550 is
powered nominally at 3V only.
November 1998
TQFP48 (7 x 7 x 1.40mm)
(Full Plastic Quad Flat Pack)
ORDER CODE : STLC7550TQF7
1/17
1 page  
STLC7550
PIN DESCRIPTION (continued)
4 - ANALOG INTERFACE (9 pins)
4.1 - DAC and ADC Positive Reference
Voltage Output (VREFP)
This pin provides the Positive Reference Voltage
used by the 16-bit converters. The reference volt-
age, VREF, is the voltage difference between the
VREFP and VREFN outputs, and its nominal value is
1.25V. VREFP should be externally decoupled with
respect to VCM.
4.2 - DAC and ADC Negative Reference
Voltage Output (VREFN)
This pin provides the Negative Reference Voltage
used by the 16-bit converters, and should be exter-
nally decoupled with respect to VCM.
4.3 - Common Mode Voltage Output (VCM)
This output pin is the common mode voltage
(AVDD - AGND)/2. This output must be decoupled
with respect to GND.
4.4 - Non-inverting Smoothing Filter Output(OUT+)
This pin is the non-inverting output of the fully
differential analog smoothing filter.
4.5 - Inverting Smoothing Filter Output (OUT-)
This pin is the inverting output of the fully differential
analog smoothing filter. Outputs OUT+ and OUT-
provide analog signals with maximum peak-to-
peak amplitude 2 x VREF, and must be followed by
an external two pole smoothing filter. The external
filter follows the internal single pole switch capaci-
tor filter. The cutoff frequency of the external filter
must be greater than two times the sampling fre-
quency (FS), so that the combined frequency re-
sponse of both the internal and external filters is flat
in the passband . The attenuator of the last output
stage can be programmed to 0dB, 6dB or infinite.
4.6 - Non-inverting Analog Input (IN+)
This pin is the differential non-inverting ADC input.
4.7 - Inverting Analog Input (IN-)
This pin is the differential inverting ADC input.
These analog inputs (IN+, IN-) are presented to the
Sigma-Delta modulator. The analog input peak-to-
peak differential signal range must be less than
2 x VREF, and must be preceded by an external
single pole anti-aliasing filter. The cut-off frequency
of the filter must be lower than one half the over-
sampling frequency. These filters should be set as
close as possible to the IN+ and IN- pins. The gain
of the first stage is programmable (see Table 3).
4.8 - Non-inverting Auxiliary Analog
Input (AUX IN+)
This pin is the differential non-inverting auxiliary ADC
input. The characteristics are same as the IN+ input.
4.9 - Inverting Auxiliary Analog Input (AUX IN-)
This pin is the differential inverting auxiliary ADC
input. The characteristics are same as the IN- input.
The input pair (IN+/IN- or AUX IN+/AUX IN-) are
software selectable.
BLOCK DIAGRAM (TQFP44)
HC0 HC1
15 14
IN+
IN-
AUXIN+
AUXIN-
OUT+
OUT-
VREFP
VREFN
VCM
27 ANALOG
28 MODULATOR
MUX
25
26
(0 + 6dB in
diff. input)
36 ATTEN.
0dB/+6dB/
37 INFINITE
18
DAC 1 BIT
First order
differential
switched
capacitor
filter
19
CLOCK
30 GENERATOR
2nd ORDER
MODULATOR
LOW-PASS
(0.425 x sampling
frequency)
LOW-PASS
(0.425 x sampling
frequency)
29 20 31
89
5 6 38
16
7
42
41
40
39
17
4
3
STLC7550
MCM
DOUT
DIN
TSTD1
TS
M/S
FS
SCLK
AVDD AGND1 AGND2
XTALOUT XTALIN
DVDD DGND RESET PWRDWN
5/17
5 Page 
STLC7550
ELECTRICAL SPECIFICATIONS
Unless otherwise noted, Electrical Characteristics are specified over the operating range.
Typical values are given for VDD = 3V, Tamb = 25°C and for nominal Master clock frequency
MCLK = 1.536MHz and oversampling ratio = 160.
Absolute Maximum Ratings (referenced to GND)
Symbol
Parameter
VDD
VI,VIN
II,IIN
IO
IOUT
Toper
Tstg
PDMAX
ESD
DC Supply Voltage
Digital or Analog Input Voltage
Digital or Analog Input Current
Digital Output Current
Analog Output Current
Operating Temperature
Storage Temperature
Maximum Power Dissipation
Electrostatic Discharge
Value
-0.3, 7.0
-0.3, VDD+0.3
±1
±20
±10
0, 70
-40, 125
200
2000
Unit
V
V
mA
mA
mA
°C
°C
mW
V
Nominal DC Characteristics (VDD = 3V ± 5%, GND = 0V, TA = 0 to 70°C unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD Supply Voltage Range
2.70 3 5.5
V
POWER SUPPLY AND COMMON MODE VOLTAGE
SINGLE POWER SUPPLY (DVDD = AVDD)
IDDA Analog Supply Current
IDDD Digital Supply Current
IDD-LP
Supply Current in Low Power Mode MCLK Stopped
MCLK Running
VCM Output Common Mode Voltage
VCM Output Voltage Load Current (see Note 1)
VDD/2-5%
6
4
1
200
VDD/2
10
VDD/2+5%
mA
mA
µA
µA
V
DIGITAL INTERFACE
VIL Low Level Input Voltage
VIH High Level Input Voltage
II Input Current VI = VDD or VI = GND
VOH High Level Output Voltage (ILOAD = -600µA)
VOL Low Level Output Voltage (ILOAD = 800µA)
-0.3 0.5 V
DVDD-0.5
V
-10 ±1 10 µA
DVDD-0.5
V
0.3 V
ANALOG INTERFACE
VREF
Tempco (VREF)
VCMO IN
VDIF IN
VOFF IN
VCMO OUT
VDIF OUT
VOFF OUT
RIN
ROUT
RL
CL
VADO OUT
Differential Reference Voltage Output
VREF = (VREFP - VREFN)
VREF Temperature Coefficient
Input Common Mode Offset Voltage = [(IN+)+(IN-)]/2 -VCM
Differential Input Voltage : [(IN+)-(IN-)] ≤ 2 x VREF
Differential Input DC Offset Voltage
Output Common Mode Voltage Offset :
(OUT+ + OUT-)/2 - VCM (see Note 1)
Differential Output Voltage : OUT+ - OUT- ≤ 2 x VREF
Differential Output DC Offset Voltage : (OUT+ - OUT-) (0000x)
Input Resistance IN+, IN- (id. AUX IN)
Output Resistance (OUT+, OUT-)
Load Resistance (OUT+, OUT-)
Load Capacitance (OUT+, OUT-)
Output A/D Modulator Voltage Offset : IN+ = IN- = VCM
1.15
-100
-100
-20
-100
100
10
-1000
1.25
200
2 x VREF
2 x VREF
50
1.35
100
100
20
100
20
+1000
V
ppm/°C
mV
Vpp
mV
mV
V
mV
kΩ
Ω
kΩ
pF
LSB
Note : 1. Device is very sensitive to noise on VCM Pin. VCM output voltage load current must be DC (<10µA). in order to drive dynamic load,
VCM must be buffered. AC variation in VCM current magnitude decrease A/D and D/A performance.
11/17
11 Page | ||
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| PDF Descargar | [ Datasheet STLC7550.PDF ] | |
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