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PDF RSC-364 Data sheet ( Hoja de datos )
| Número de pieza | RSC-364 | |
| Descripción | (RSC-360 / RSC-364) Speech Recognition Microcontroller | |
| Fabricantes | Sensory | |
| Logotipo |  |
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heet4U.com Speech RecognitionRMSicCro-c3o0n0tr/o3l6le4rGeneral Description
SThe RSC-300/364, from the Interactive Speech TM
tafamily of products, is designed specifically for
aspeech applications in consumer electronic
.Dproducts.
wThe RSC-300/364 combines an 8-bit processor with
wneural-net algorithms to provide high-quality
w speaker-independent speech recognition, speaker-
mdependent speech recognition, and speaker
verification. The chip also supports speech
osynthesis, voice record/playback, 4-voice music
.csynthesis, and system control. This CMOS device
includes on-chip RAM, ROM (RSC-364 only), 16
general-purpose I/O lines, A/D and D/A converters,
Ua microphone pre-amplifier, and a 4-MIPS dedicated
processor. The RSC-300 is designed for ROM-less
t4applications that need more ROM space and
consequently use off-chip memory.
eIn addition to providing the horsepower needed to
eperform speech recognition and speech synthesis,
the processor has sufficient cycles available for
hgeneral-purpose product control. The RSC-300/364
Development Kit allows developers to create
Scustom applications. The Development Kit includes
an assembler, linker, simulator, hardware
tadevelopment platform, and library of Sensory
technology object code.
aThe highly integrated nature of this chip reduces
external parts count. A complete system may be
.Dbuilt with only a few passive components in addition
to a battery, speaker, and microphone. Low power
requirements and low-voltage operation make the
wRSC-300/364 an ideal solution for battery-powered
and hand-held devices.
wThe RSC-300/364 uses a pre-trained neural
w mnetwork to perform speaker-independent speech
.corecognition, while high-quality speech synthesis is
achieved using a time-domain compression scheme
Uthat improves on conventional ADPCM. Four-voice
t4music synthesis allows multiple, simultaneous
einstruments for harmonizing. Automatic Gain
eControl can compensate for people not optimally
hpositioned with respect to the microphone or for
Speople who speak too softly or loudly.
DATA SHEET
Features
High-Performance Processor
4-MIPS performance at 14.32 MHz
16 general purpose I/O lines
Interrupts, timers and counters
Fully static operation; clock rate: DC to 14.32
MHz
Highly-Integrated Single-Chip Solution
Internal 64 kB of ROM (364 only), 2.5 kB of
RAM
12 bit A/D (Analog to Digital) converter
Microphone Pre-amplifier
Internal 32kHz secondary timer
24 x 24 Multiplier
Can store 6 Speaker Dependent words on-
chip
Low Power Requirements
Requires single 2.85V to 5.25V power supply
~10mA operating current at 3V
Low Power 32kHz oscillator
Power-down current less than 5 µA
High-Quality Recognition and Synthesis
Recognition accuracy: better than 97%
(Speaker Independent) and 99% (Speaker
Dependent).
Synthesis data rates from 5,000-15,000 bits
per second
4-voice music synthesis capabilities
AGC control compensates for variations in
input signal
Easily Expanded to Larger-Scale Systems
Separate 16-bit Address and 8-bit Data
buses compatible with common memory
components
Separate Code and Data address spaces
and memory strobes
www.Data© 2001 Sensory Inc.
P/N 80-0165-O
1
1 page  
Data Sheet
RSC-300/364
Rsc-300/364 Hardware Specifications
Architectural Overview of the RSC-300/364
The RSC-300/364 is a highly integrated device
that combines:
• An 8-bit RISC microprocessor.
• On-chip ROM (64 Kbytes, RSC-364 only),
Register RAM (448 bytes), Data RAM (2
Kbytes) and the ability to address off-chip
RAM or ROM.
• Analog-to-digital converter, digital-to-
analog converter, and a pulse width
modulator.
• A microphone pre-amplifier
The RSC-300/364 has an external memory
interface for accessing external RAMs, ROMs
or other parallel memory devices. The RSC-
364 also has an internal ROM that can be
enabled or disabled (partially or fully) by pin
inputs (signals -XMH, -XML; See figure 4). ).
When the internal ROM of the RSC-364 is
disabled, its performance is identical to the
RSC-300. With the RSC-364, the entire
program must reside in the internal masked
ROM. External memory can only be used to
store data.
AiFE1
AiFE2
AiNØ
AiN1
PRE-AMP
AOFE1
AOFE2
AOFE3
DACOUT
ADC
DAC
BUFOUT/
ANALOG
CONTROL
PWM
XI1, XO1
PULSE
WIDTH
MODULATOR
OSC1
SPEECH
PROCESSING
UNIT
TIMER1
XI2, XO2
TIMER2
OSC2
P0.0-P0.7
EXTERNAL
MEMORY
INTERFACE
2K TECHNOLOGY
SRAM
REGISTER SPACE
448 bytes
A[15:0]
D[7:0]
-RDC
-WRC
-RDD
-WRD
STACK SPACE
8 levels
CPU
INTERNAL ROM (RSC-364)
32K x 8
-XMH
HIGH
32K x 8 LOW
-XML
TIMING AND
CONTROL
BREAK POINT
REGISTER
-RESET
-TE1/
PWM
The 8-bit processor can directly access 448
P1.0-P1.7
on-chip general-purpose registers (RAM), and
32 additional Special Functions Registers
(SFRs). The instruction set accessing these
registers is completely symmetrical, allowing
Figure 1 – RSC-300/364 Block Diagram
movs, arithmetic, and logical operations with
any register as the destination. Two bi-directional ports provide 16 general-purpose I/O pins to communicate
with external devices (See page 9). The RSC-300/364 has a high frequency (14.32 MHz) oscillator as well as a
low frequency (32,768 Hz) oscillator. The processor clock can be selected from either source, with a selectable
divider value. Sensory’s technology code requires the use of the 14.32 MHz clock. There are two
programmable 8-bit counters / timers, one derived from each oscillator. A variety of wait state configurations
allow fast code execution and easy interfacing to slow peripheral memories.
An inexpensive electret microphone connects directly to the microphone input of the RSC-300/364. The internal
preamplifier converts the tiny microphone signal to a level suitable for Analog-to-Digital Conversion. (ADC), The
RSC-300/364 uses a Sample and Hold (SH) circuit and ADC converter to convert the amplified analog speech
signal into digital data. The chip may also be used with line-level inputs. The output audio signal of the RSC-
300/364 is derived either from a DAC (Digital-to-Analog Converter) or a PWM (Pulse Width Modulator).
In addition to its on-chip ROM (RSC-364 only) and RAM, the RSC-300/364 has 8 data lines (D[7:0]) and 16
address lines (A[15:0]), along with associated control signals (-RDC, -RDD, -WRC, -WRD, -XML, -XMH) for
interfacing to external memory. The memory control signals on the RSC-300/364 and the processor instruction
set provide independent Code and Data spaces, allowing configuration of systems up to 192 Kbytes with no
additional hardware decoding. The RSC-300/364 features 16 general-purpose I/O pins (Px.y) for product and
memory bank control.
© 2002 Sensory Inc.
P/N 80-0165-O
5
5 Page 
Data Sheet
RSC-300/364
After source selection, the processor clock can be divided-down in order to limit power consumption. Bits 3 and
4 of the Clock Control Register determine the divisor for the processor clock. Between zero and seven wait
states must also be selected for the processor clock. Wait states are inserted on reads or writes to all addresses
except Register Space RAM and, under certain configurations, internal ROM (RSC-364 only).
Sensory technology code must run with a processor clock of 14.32 MHz, a clock divisor of one, and one wait
state. This creates internal RAM cycles of 70 nsec duration and internal ROM (RSC-364 only) or external cycles
of 140 nsec duration. Careful design of external decoding logic and close analysis of gate delays may allow
operation with Code Space memories having 120 nsec access times. Additional wait states may be selected for
external Data Space access.
Timers and Counters
The two independent oscillators of the RSC-300/364 provide counts to two internal timers. Each of the two
timers consists of an 8-bit reload value register and an 8-bit up-counter. The reload register is readable and
writeable by the processor. The counter is readable with precaution taken against a counter change in the
middle of a read. If the processor writes to the counter, the data is ignored. Instead, the counter is preset to the
reload register value. That is, any write to a counter will cause it to be reloaded. This is the usual way of
initializing the counter. When the timer overflows from FF to 00, a pulse is generated that sets IRQ #0 (timer #1)
or IRQ #1 (timer #2). If the corresponding IMR bit is set and the Global Interrupt Bit is set, an interrupt will be
generated. Instead of overflowing to 00, the counter is automatically reloaded on each overflow.
For example, if the reload value is 0FAh, the counter will count as follows:
0FAh, 0FBh, 0FCh, 0FDh, 0FEh, 0FFh, 0FAh, 0FBh etc.
The overflow pulse is generated during the period after the counter value was 0FFh.
Timer #2 may be used as a wakeup when the processor has powered-down.
Refer to the following registers for more information about using timers and counters:
T1R:
T1V:
T2R:
T2V:
Timer 1 Reload Register (page 28)
Timer 1 Counter Register (page 28)
Timer 2 Reload Register (page 29)
Timer 2 Counter Register (page 29)
Power Down and Wake-Up Operation
The RSC-300/364 can be powered down through software by setting the PD bit (bit7) of the Clock Control
Register (See page 33). Setting this bit halts the processor until a “wakeup” event clears the bit. The instruction
that causes the power down event may also set or clear other bits in the Clock Control Register to enable or
disable any of the clocks, and to select a clock to be used as the processor clock upon wakeup. A wakeup event
can be generated from either of two sources:
bit transition(s) of port 0 or port 1 pins, or
an overflow pulse from timer 2.
For low power consumption, oscillator #1 (bit 0) and the FC clock (bit 5) should always be disabled during power
down. Oscillator #2 (bit 1) must be enabled if the wakeup condition is a timer 2 event. If the wakeup event is an
IO pin event, all clocks should be disabled for lowest power consumption.
If oscillator #1 is disabled during power down, and the selected processor clock source is oscillator #1, then a
wakeup event will require that oscillator #1 be started and stabilized before its output can be used as the
processor clock. The oscillator is started when the wakeup event clears bit 0 of the Clock Control Register, but
the processor clock is delayed by 10 milliseconds to assure stability.
© 2002 Sensory Inc.
P/N 80-0165-O
11
11 Page | ||
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| PDF Descargar | [ Datasheet RSC-364.PDF ] | |
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